专利名称：Fractional divider using a calibrated digital-to-time converter
发明人：Song Gao,Brian Buell,Katherine T. Blinick申请号：US15185378申请日：20160617公开号：US09678481B1公开日：20170613
专利附图：
摘要：An apparatus comprising a first circuit and a second circuit. The first circuit maybe configured to generate a divided clock signal and a control signal in response to (i) aninput clock signal and (ii) a configuration signal. The second circuit may be configured to
generate an output clock signal in response to (i) the control signal and (ii) the dividedclock signal. The second circuit may add a delay to one or more edges of the outputclock signal by engaging one or more of a plurality of capacitances. A number of thecapacitances engaged may be selected to reduce jitter on the output clock signal. Thecapacitances may be used each cycle to calibrate the output clock signal.
申请人：Integrated Device Technology, Inc.
地址：San Jose CA US
国籍：US
代理人：Christopher P. Maiorana P.C.
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