FEATURES
Integrated Precision Reference 2.5V Full-Scale 10ppm/°C (LTC2631-L) 4.096V Full-Scale 10ppm/°C (LTC2631-H)n Maximum INL Error: 1LSB (LTC2631A-12)n Bidirectional Reference: Input or 10ppm/°C Outputn 400kHz I2C™ Interfacen Nine Selectable Addresses (LTC2631-Z)n Low Noise (0.7mVP-P, 0.1Hz to 200kHz)n Guaranteed Monotonic Over Temperaturen 2.7V to 5.5V Supply Range (LTC2631-L)n Low Power Operation: 180μA at 3Vn Power Down to 1.8μA Maximum (C and I Grades)n Power-On Reset to Zero or Mid-Scale Optionsn Double-Buffered Data Latchesn Guaranteed Operation From –40°C to 125°C (H-Grade)n 8-Lead TSOT-23 (ThinSOT™) PackagenLTC2631Single 12-/10-/8-Bit I2CVOUT DACs with10ppm/°C Reference ESCRIPTIOND
The LTC®2631 is a family of 12-, 10-, and 8-bit voltage-output DACs with an integrated, high accuracy, low-drift reference in an 8-lead TSOT-23 package. It has a rail-to-rail output buffer that is guaranteed monotonic.The LTC2631-L has a full-scale output of 2.5V, and oper-ates from a single 2.7V to 5.5V supply. The LTC2631-H has a full-scale output of 4.096V, and operates from a 4.5V to 5.5V supply. A 10ppm/°C reference output is available at the REF pin.Each DAC can also operate in External Reference mode, in which a voltage supplied to the REF pin sets the full-scale output.The LTC2631 DACs use a 2-wire, I2C-compatible serial interface. The LTC2631 operates in both the standard mode (clock rate of 100kHz) and the fast mode (clock rate of 400kHz).The LTC2631 incorporates a power-on reset circuit. Op-tions are available for reset to zero-scale or reset to mid-scale after power-up.L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. I2C and ThinSOT are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5396245, 5859606, 6891433, 6937178 and 7414561.APPLICATIONS
Mobile Communicationsn Process Control and Industrial Automationn Automatic Test Equipmentn Portable Equipmentn Automotiven Optical NetworkingnBLOCK DIAGRAM
CA0I2CADDRESSDECODE(LTC2631-M)VCCINTERNALREFERENCEREFIntegral Nonlinearity (LTC2631A-LM12)REF_SEL1.0
VCC = 3VVFS = 2.5V
SWITCHINL (LSB)VOUTSCLI2CINTERFACESDACONTROLDECODE LOGIC0.5
RESISTORDIVIDER0
DACREFINPUTREGISTERDACREGISTER–0.5
DAC–1.0
GND2631 TA01010242048CODE
30724095
2631 TA01b
2631fb1
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LTC2631ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)Supply Voltage (VCC) ...................................–0.3V to 6VREF_SEL, SCL, SDA .....................................–0.3V to 6VVOUT, CA0, CA1, REF .........–0.3V to Min(VCC + 0.3V, 6V)Operating Temperature Range LTC2631C ................................................0°C to 70°C LTC2631I..............................................–40°C to 85°C LTC2631H (Note 3) ............................–40°C to 125°C Maximum Junction Temperature...........................150°CStorage Temperature Range ...................–65°C to 150°CLead Temperature (Soldering, 10 sec) ..................300°CPIN CONFIGURATION
LTC2631-ZCA0 1SCL 2SDA 3GND 4TOP VIEW8 CA17 VOUT6 REF5 VCCLTC2631-MCA0 1SCL 2SDA 3GND 4TOP VIEW8 REF_SEL7 VOUT6 REF5 VCCTS8 PACKAGE8-LEAD PLASTIC TSOT-23TJMAX = 150°C (NOTE 6), θJA = 195°C/WTS8 PACKAGE8-LEAD PLASTIC TSOT-23TJMAX = 150°C (NOTE 6), θJA = 195°C/W2631fb2
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LTC2631ORDER INFORMATION
LTC2631ACTS8–LM12#TRMPBFLEAD FREE DESIGNATORTAPE AND REELTR = 2,500-Piece Tape and ReelTRM = 500-Piece Tape and ReelRESOLUTION12 = 12-Bit 10 = 10-Bit 8 = 8-Bit POWER-ON RESETM = Reset to Mid-ScaleZ = Reset to Zero-ScaleFULL-SCALE VOLTAGE, INTERNAL REFERENCE MODEL = 2.5VH = 4.096VPACKAGE TYPETS8 = 8-Lead Plastic TSOT-23TEMPERATURE GRADEC = Commercial Temperature Range (0°C to 70°C)I = Industrial Temperature Range (–40°C to 85°C)H = Automotive Temperature Range (–40°C to 125°C)ELECTRICAL GRADE (OPTIONAL)A = ±1LSB Maximum INL (12-Bit)PRODUCT PART NUMBERConsult LTC Marketing for information on non-standard lead based fi nish parts.For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/2631fb3
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LTC2631PRODUCT SELECTION GUIDE
PART NUMBERLTC2631A-LM12LTC2631A-LZ12LTC2631A-HM12LTC2631A-HZ12LTC2631-LM12LTC2631-LM10LTC2631-LM8LTC2631-LZ12LTC2631-LZ10LTC2631-LZ8LTC2631-HM12LTC2631-HM10LTC2631-HM8LTC2631-HZ12LTC2631-HZ10LTC2631-HZ8VFS WITH INTERNAL PART MARKING*REFERENCELTDHFLTDHGLTDHHLTDHJLTDHFLTDHKLTDHQLTDHGLTDHMLTDHRLTDHHLTDHNLTDHSLTDHJLTDHPLTDHT2.5V • (4095/4096)2.5V • (4095/4096)4.096V • (4095/4096)4.096V • (4095/4096)2.5V • (4095/4096)2.5V • (1023/1024)2.5V • (255/256)2.5V • (4095/4096)2.5V • (1023/1024)2.5V • (255/256)4.096V • (4095/4096)4.096V • (1023/1024)4.096V • (255/256)4.096V • (4095/4096)4.096V • (1023/1024)4.096V • (255/256)POWER-ON RESET TO CODEPIN 8Mid-ScaleZeroMid-ScaleZeroMid-ScaleMid-ScaleMid-ScaleZeroZeroZeroMid-ScaleMid-ScaleMid-ScaleZeroZeroZeroREF_SELCA1REF_SELCA1REF_SELREF_SELREF_SELCA1CA1CA1REF_SELREF_SELREF_SELCA1CA1CA1RESOLUTION12-Bit12-Bit12-Bit12-Bit12-Bit10-Bit8-Bit12-Bit10-Bit8-Bit12-Bit10-Bit8-Bit12-Bit10-Bit8-BitVCC2.7V – 5.5V2.7V – 5.5V4.5V – 5.5V4.5V – 5.5V2.7V – 5.5V2.7V – 5.5V2.7V – 5.5V2.7V – 5.5V2.7V – 5.5V2.7V – 5.5V4.5V – 5.5V4.5V – 5.5V4.5V – 5.5V4.5V – 5.5V4.5V – 5.5V4.5V – 5.5VMAXIMUM INL±1LSB±1LSB±1LSB±1LSB±2.5LSB±1LSB±0.5LSB±2.5LSB±1LSB±0.5LSB±2.5LSB±1LSB±0.5LSB±2.5LSB±1LSB±0.5LSB*The temperature grade is identifi ed by a label on the shipping container.2631fb4
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LTC2631E LECTRICAL CHARACTERISTICS The l denotes the specifi cations which apply over the full operating ed.temperature range, otherwise specifi cations are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specifiLTC2631-LM12/-LM10/-LM8/-LZ12/-LZ10/-LZ8, LTC2631A-LM12/-LZ12 (VFS = 2.5V)LTC2631-8SYMBOLPARAMETERDC PerformanceResolutionMonotonicityDNLINLZSEVOSVOSTCFSEVFSTCDifferential NonlinearityIntegral NonlinearitylLTC2631-10LTC2631-12LTC2631A-12UNITSBitsBits±1±0.50.5±0.5±10±0.08±0.4±15±5LSBLSBmVmVμV/°C%FSRCONDITIONSMIN88TYPMAXMINTYPMAXMINTYP1010±0.5±0.5±0.20.5±0.5±10±0.08±0.4±15±5±10.5±0.5±101212MAXMINTYPMAX1212±1±2.55±5VCC = 3V, Internal Ref. (Note 4)lVCC = 3V, Internal Ref. (Note 4)lVCC = 3V, Internal Ref. (Note 4)lll±0.05±0.50.5±0.5±105±5Zero-Scale ErrorVCC = 3V, Internal Ref., Code = 0Offset ErrorVCC = 3V, Internal Ref. (Note 5)VOS Temperature VCC = 3V, Internal Ref.Coeffi cient(Note 5)Full-Scale ErrorFull-Scale Voltage Temperature Coeffi cientVCC = 3V, Internal Ref. (Note 15)VCC = 3V, Internal Ref. (Note 10) C-Grade I-Grade H-Gradelll±0.08±0.4±0.08±0.4±10±10±100.0090.0160.0090.016±10±10±100.0350.0640.0350.064±10±10±100.140.2560.140.256±10±10±10ppm/°Cppm/°Cppm/°CLoad RegulationInternal Ref., Mid-Scale, VCC = 3V ±10%, –5mA ≤ IOUT ≤ 5mA, VCC = 5V ±10%, –10mA ≤ IOUT ≤ 10mAROUTDC Output ImpedanceInternal Ref., Mid-Scale, VCC = 3V ±10%, –5mA ≤ IOUT ≤ 5mA, VCC = 5V ±10%, –10mA ≤ IOUT ≤ 10mA0.140.256LSB/mA0.140.256LSB/mAll0.090.1560.090.1560.090.1560.090.1560.090.1560.090.1560.090.1560.090.156ΩΩSYMBOLVOUTPSRISCPARAMETERDAC Output SpanPower Supply RejectionShort-Circuit Output Current (Note 6) Sinking SourcingPositive Supply VoltageSupply Current (Note 7)CONDITIONSExternal ReferenceInternal ReferenceVCC = 3V ±10% or 5V ±10%VFS = VCC = 5.5V Zero-Scale; VOUT shorted to VCC Full-Scale; VOUT shorted to GNDFor Specifi ed PerformanceVCC = 3V, VREF = 2.5V, External ReferenceVCC = 3V, Internal ReferenceVCC = 5V, VREF = 2.5V, External ReferenceVCC = 5V, Internal ReferenceVCC = 5V, C-Grade, I-GradeVCC = 5V, H-GradelllllllllMINTYP0 to VREF0 to 2.5–8027–28MAXUNITSVVdB48–485.5mAmAVμAμAμAμAμAμA2631fbPower SupplyVCCICC2.71501801601900.60.62002402102601.84ISDSupply Current in Power-Down Mode (Note 7)5
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LTC2631 The l denotes the specifi cations which apply over the full operating ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifi cations are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specifi ed.LTC2631-LM12/-LM10/-LM8/-LZ12/-LZ10/-LZ8, LTC2631A-LM12/-LZ12 (VFS = 2.5V)SYMBOLReference InputInput Voltage RangeResistanceCapacitanceIREFReference OutputOutput VoltageReference Temperature Coeffi cientOutput ImpedanceCapacitive Load DrivingShort-Circuit CurrentDigital I/OVILVIHVIL(CAn)VIH(CAn)RINHRINLRINFVOLtOFtSPIINCINCBCCAnLow Level Input Voltage (SDA and SCL)Low Level Input Voltage on CAn (n = 0, 1)High Level Input Voltage on CAn (n = 0, 1)Resistance from CAn (n = 0, 1) to VCC to Set CAn = VCCResistance from CAn (n = 0, 1) to GND to Set CAn = GNDResistance from CAn (n = 0, 1)to VCC or GND to Set CAn = FloatLow Level Output VoltageOutput Fall TimePulse Width of Spikes Suppressed by Input FilterInput LeakageI/O Pin CapacitanceCapacitive Load for Each Bus LineExternal Capacitive Load on AddressPin CAn (n = 0, 1)0.1VCC ≤ VIN ≤ 0.9VCC(Note 8)(Note 14)See Test Circuit 1See Test Circuit 1See Test Circuit 2See Test Circuit 2See Test Circuit 2Sink Current = 3mAVO = VIH(MIN) to VO = VIL(MAX), CB = 10pF to 400pF (Note 12)lllllllllllllllllPARAMETERCONDITIONSMIN0160TYPMAXVCCUNITSVkΩpFμAVppm/°CkΩμFmA1907.50.0052200.11.260Reference Current, Power-Down ModeDAC Powered Downl1.2401.250±100.510VCC = 5.5V; REF Shorted to GND–0.50.7VCC2.50.3VCC0.15VCC0.85VCC10102020 + 0.1CB00.425050±11040010VVVVkΩkΩMΩVnsnsμApFpFpFHigh Level Input Voltage (SDA and SCL)(Note 11)2631fb6
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LTC2631E LECTRICAL CHARACTERISTICS The l denotes the specifi cations which apply over the full operating ed.temperature range, otherwise specifi cations are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specifiLTC2631-LM12/-LM10/-LM8/-LZ12/-LZ10/-LZ8, LTC2631A-LM12/-LZ12 (VFS = 2.5V)SYMBOLAC PerformancetSSettling TimeVCC = 3V (Note 9)±0.39% (±1LSB at 8-Bits)±0.098% (±1LSB at 10-Bits)±0.024% (±1LSB at 12-Bits)3.23.84.11500At Mid-Scale TransitionExternal ReferenceAt f = 1kHz, External ReferenceAt f = 10kHz, External ReferenceAt f = 1kHz, Internal ReferenceAt f = 10kHz, Internal Reference0.1Hz to 10Hz, External Reference0.1Hz to 10Hz, Internal Reference0.1Hz to 200kHz, External Reference0.1Hz to 200kHz, Internal Reference, CREF = 0.33μF2.13001401301601502020650670μsμsμsV/μspFnV•skHznV√HznV√HznV√HznV√HzμVP-PμVP-PμVP-PμVP-PPARAMETERCONDITIONSMINTYPMAXUNITSVoltage-Output Slew RateCapacitance Load DrivingGlitch ImpulseMultiplying BandwidthenOutput Voltage Noise DensityOutput Voltage NoiseTIMING CHARACTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VCC = 2.7V to 5.5V. (See Figure 1) (Note 13).LTC2631-LM12/-LM10/-LM8/-LZ12/-LZ10/-LZ8, LTC2631A-LM12/-LZ12 (VFS = 2.5V)SYMBOLfSCLtHD(STA)tLOWtHIGHtSU(STA)tHD(DAT)tSU(DAT)trtftSU(STO)tBUFPARAMETERSCL Clock FrequencyHold Time (Repeated) Start ConditionLow Period of the SCL Clock PinHigh Period of the SCL Clock PinSet-Up Time for a Repeated Start ConditionData Hold TimeData Set-Up TimeRise Time of Both SDA and SCL SignalsFall Time of Both SDA and SCL SignalsSet-Up Time for Stop ConditionBus Free Time Between a Stop and Start Condition(Note 12)(Note 12)CONDITIONSlllllllllllMIN00.61.30.60.6010020 + 0.1CB20 + 0.1CB0.61.3TYPMAX400UNITSkHzμsμsμsμs0.9300300μsnsnsnsμsμs2631fb7
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LTC2631 The l denotes the specifi cations which apply over the full operating ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifi cations are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specifi ed.LTC2631-HM12/-HM10/-HM8/-HZ12/-HZ10/-HZ8, LTC2631A-HM12/-HZ12 (VFS = 4.096V)LTC2631-8SYMBOLPARAMETERDC PerformanceResolutionMonotonicityDNLINLZSEVOSVOSTCFSEVFSTCDifferential NonlinearityIntegral NonlinearityZero-Scale ErrorOffset ErrorVCC = 5V, Internal Ref. (Note 4)VCC = 5V, Internal Ref. (Note 4)VCC = 5V, Internal Ref. (Note 4)llllLTC2631-10LTC2631-12LTC2631A-12UNITSBitsBits±1±0.50.5±0.5±10±0.08±0.4±10±10±10±15±5LSBLSBmVmVμV/°C%FSRppm/°Cppm/°Cppm/°CCONDITIONSMIN88TYPMAXMINTYPMAXMINTYP1010±0.5±0.5±0.20.5±0.5±10±0.08±0.4±10±10±100.0220.040.090.156±15±5±10.5±0.5±101212MAXMINTYPMAX1212±1±2.55±5±0.05±0.50.5±0.5±10±0.08±0.4±10±10±100.0060.010.090.1565±5VCC = 5V, Internal Ref., Code = 0lVCC = 5V, Internal Ref. (Note 5)lVOS Temperature VCC = 5V, Internal Ref. (Note 5)Coeffi cientFull-Scale ErrorFull-Scale Voltage Temperature Coeffi cientLoad RegulationVCC = 5V, Internal Ref. (Note 15)lVCC = 5V, Internal Ref. (Note 10) C-Grade I-Grade H-GradelVCC = 5V ±10%, Internal Ref.Mid-Scale, –10mA ≤ IOUT ≤ 10mAlVCC = 5V ±10%, Internal Ref.Mid-Scale, –10mA ≤ IOUT ≤ 10mA±0.08±0.4±10±10±100.090.160.090.16LSB/mA0.090.156ΩROUTDC Output Impedance0.090.156SYMBOLVOUTPSRISCPARAMETERDAC Output SpanPower Supply RejectionShort-Circuit Output Current (Note 6) Sinking SourcingPositive Supply VoltageSupply Current (Note 7)CONDITIONSExternal ReferenceInternal ReferenceVCC = 5V ±10%VFS = VCC = 5.5V Zero-Scale; VOUT shorted to VCC Full-Scale; VOUT shorted to GNDFor Specifi ed PerformanceVCC = 5V, VREF = 4.096V, External ReferenceVCC = 5V, Internal ReferencelllllllMINTYP0 to VREF0 to 4.096–8027–28MAXUNITSVVdB48–485.5mAmAVμAμAμAμAPower SupplyVCCICCISD4.51602000.60.62202701.84Supply Current in Power-Down Mode VCC = 5V, C-Grade, I-Grade(Note 7)VCC = 5V, H-Grade2631fb8
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LTC2631E LECTRICAL CHARACTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specifi ed.LTC2631-HM12/-HM10/-HM8/-HZ12/-HZ10/-HZ8, LTC2631A-HM12/-HZ12 (VFS = 4.096V)SYMBOLReference InputInput Voltage RangeResistanceCapacitanceIREFReference OutputOutput VoltageReference Temperature Coeffi cientOutput ImpedanceCapacitive Load DrivingShort-Circuit CurrentDigital I/OVILVIHVIL(CAn)VIH(CAn)RINHRINLRINFVOLtOFtSPIINCINCBCCAnLow Level Input Voltage (SDA and SCL)Low Level Input Voltage on CAn (n = 0, 1)High Level Input Voltage on CAn (n = 0, 1)Resistance from CAn (n = 0, 1) to VCC to Set CAn = VCCResistance from CAn (n = 0, 1) to GND to Set CAn = GNDResistance from CAn (n = 0, 1)to VCC or GND to Set CAn = FloatLow Level Output VoltageOutput Fall TimePulse Width of Spikes Suppressed by Input FilterInput LeakageI/O Pin CapacitanceCapacitive Load for Each Bus LineExternal Capacitive Load on AddressPin CAn (n = 0, 1)0.1VCC ≤ VIN ≤ 0.9VCC(Note 8)(Note 14)See Test Circuit 1See Test Circuit 1See Test Circuit 2See Test Circuit 2See Test Circuit 2Sink Current = 3mAVO = VIH(MIN) to VO = VIL(MAX), CB = 10pF to 400pF (Note 12)lllllllllllllllllPARAMETERCONDITIONSMIN0160TYPMAXVCCUNITSVkΩpFμAVppm/°CkΩμFmA1907.50.0052200.12.064Reference Current, Power-Down ModeDAC Powered Downl2.0322.048±100.510VCC = 5.5V; REF Shorted to GND–0.50.7VCC4.30.3VCC0.15VCC0.85VCC10102020 + 0.1CB00.425050±11040010VVVVkΩkΩMΩVnsnsμApFpFpFHigh Level Input Voltage (SDA and SCL)(Note 11)2631fb9
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LTC2631 The l denotes the specifi cations which apply over the full operating ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifi cations are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specifi ed.LTC2631-HM12/-HM10/-HM8/-HZ12/-HZ10/-HZ8, LTC2631A-HM12/-HZ12 (VFS = 4.096V)SYMBOLAC PerformancetSSettling TimeVCC = 5V (Note 9)±0.39% (±1LSB at 8-Bits)±0.098% (±1LSB at 10-Bits)±0.024% (±1LSB at 12-Bits)3.74.24.61500At Mid-Scale TransitionExternal ReferenceAt f = 1kHz, External ReferenceAt f = 10kHz, External ReferenceAt f = 1kHz, Internal ReferenceAt f = 10kHz, Internal Reference0.1Hz to 10Hz, External Reference0.1Hz to 10Hz, Internal Reference0.1Hz to 200kHz, External Reference0.1Hz to 200kHz, Internal Reference, CREF = 0.33μF3.03001401302102002020650670μsμsμsV/μspFnV•skHznV√HznV√HznV√HznV√HzμVP-PμVP-PμVP-PμVP-PPARAMETERCONDITIONSMINTYPMAXUNITSVoltage-Output Slew RateCapacitance Load DrivingGlitch ImpulseMultiplying BandwidthenOutput Voltage Noise DensityOutput Voltage Noise2631fb10
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LTC2631TIMING CHARACTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VCC = 4.5V to 5.5V. (See Figure 1) (Note 13).LTC2631-HM12/-HM10/-HM8/-HZ12/-HZ10/-HZ8, LTC2631A-HM12/-HZ12 (VFS = 4.096V)SYMBOLfSCLtHD(STA)tLOWtHIGHtSU(STA)tHD(DAT)tSU(DAT)trtftSU(STO)tBUFPARAMETERSCL Clock FrequencyHold Time (Repeated) Start ConditionLow Period of the SCL Clock PinHigh Period of the SCL Clock PinSet-Up Time for a Repeated Start ConditionData Hold TimeData Set-Up TimeRise Time of Both SDA and SCL SignalsFall Time of Both SDA and SCL SignalsSet-Up Time for Stop ConditionBus Free Time Between a Stop and Start Condition(Note 12)(Note 12)CONDITIONSlllllllllllMIN00.61.30.60.6010020 + 0.1CB20 + 0.1CB0.61.3TYPMAX400UNITSkHzμsμsμsμs0.9300300μsnsnsnsμsμsNote 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltages are with respect to GND. Note 3: High temperatures degrade operating lifetimes. Operating lifetime is derated at temperatures greater than 105°C.Note 4: Linearity and monotonicity are defi ned from code kL to code N 2– 1, where N is the resolution and kL is given by kL = 0.016 • (2N/ VFS), rounded to the nearest whole code. For VFS = 2.5V and N = 12, kL = 26 and linearity is defi ned from code 26 to code 4,095. For VFS = 4.096V and N = 12, kL = 16 and linearity is defi ned from code 16 to code 4,095. Note 5: Inferred from measurement at code 16 (LTC2631-12), code 4 (LTC2631-10) or code 1 (LTC2631-8), and at full-scale.Note 6: This IC includes current limiting that is intended to protect the device during momentary overload conditions. Junction temperature can exceed the rated maximum during current limiting. Continuous operation above the specifi ed maximum operating junction temperature may impair device reliability. Note 7: Digital inputs at 0V or VCC.Note 8: Guaranteed by design and not production tested.Note 9: Internal Reference mode. DAC is stepped 1/4 scale to 3/4 scale and 3/4 scale to 1/4 scale. Load is 2kΩ in parallel with 100pF to GND.Note 10: Temperature coeffi cient is calculated by dividing the maximum change in output voltage by the specifi ed temperature range.Note 11: Maximum VIH = VCC(MAX) + 0.5VNote 12: CB = capacitance of one bus line in pFNote 13: All values refer to VIH = VIH(MIN) and VIL = VIL(MAX) levels.Note 14: Minimum VIL exceeds the Absolute Maximum rating. This condition won’t damage the IC, but could degrade performance.Note 15: Full-scale error is determined using the reference voltage measured at the REF pin.2631fb11
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LTC2631TYPICAL PERFORMANCE CHARACTERISTICS
LTC2631-L12 (Internal Reference, VFS = 2.5V)Integral Nonlinearity (INL)1.0
VCC = 3V1.0
VCC = 3V0.5DNL (LSB)VREF (V)1.255
TA = 25°C, unless otherwise noted.Reference Output Voltage vs Temperature1.260
VCC = 3VDifferential Nonlinearity (DNL)0.5INL (LSB)001.250
–0.5–0.51.245
–1.0
010242048CODE
30724095
2631 G01
–1.0
010242048CODE
30724095
2631 G02
1.240
–50–25
0
255075100125150TEMPERATURE (°C)
2631 G03
INL vs Temperature1.0
VCC = 3V0.5INL (LSB)0.5DNL (LSB)1.0
DNL vs Temperature2.52
VCC = 3VFS OUTPUT VOLTAGE (V)2.51
Full-Scale Output Voltage vs TemperatureVCC = 3VINL (POS)DNL (POS)0
DNL (NEG)–0.5
0
INL (NEG)–0.5
2.50
2.49
–1.0
–50–25
0
255075100125150TEMPERATURE (°C)
2631 G04
–1.0
–50–25
0
255075100125150TEMPERATURE (°C)
2631 G05
2.48
–50–25
0
255075100125150TEMPERATURE (°C)
2631 G06
Settling to ±1LSB9th CLOCK OF3rd DATA BYTESettling to ±1LSB3/4 SCALE TO 1/4 SCALE STEPVCC = 3V, VFS = 2.5VRL = 2k, CL = 100pFAVERAGE OF 256 EVENTSSCL2V/DIV
VOUT1LSB/DIV
4.1μs3.6μsVOUT1LSB/DIV
1/4 SCALE TO 3/4 SCALE STEPVCC = 3V, VFS = 2.5VRL = 2k, CL = 100pFAVERAGE OF 256 EVENTS2μs/DIV
2631 G07
9th CLOCK OF3rd DATA BYTESCL2V/DIV
2μs/DIV
2631 G08
2631fb12
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LTC2631TYPICAL PERFORMANCE CHARACTERISTICS
LTC2631-H12 (Internal Reference, VFS = 4.096V)Integral Nonlinearity (INL)1.0
VCC = 5V1.0
TA = 25°C, unless otherwise noted.Reference Output Voltage vs Temperature2.068
VCC = 5V2.058VREF (V)Differential Nonlinearity (DNL)VCC = 5V0.5
DNL (LSB)INL (LSB)0.5
002.048
–0.5–0.52.038
–1.0
010242048CODE
30724095
2631 G09
–1.0
010242048CODE
30724095
2631 G10
2.028
–50–25
0
255075100125150TEMPERATURE (°C)
2631 G11
INL vs Temperature1.0
VCC = 5V0.5INL (LSB)0.5DNL (LSB)1.0
DNL vs Temperature4.115
VCC = 5VFS OUTPUT VOLTAGE (V)4.105
Full-Scale Output Voltage vs TemperatureVCC = 5VINL (POS)DNL (POS)0
DNL (NEG)–0.5
0
INL (NEG)–0.5
4.095
4.085
–1.0
–50–25
0
255075100125150TEMPERATURE (°C)
2631 G12
–1.0
–50–25
0
255075100125150TEMPERATURE (°C)
2631 G13
4.075
–50–25
0
255075100125150TEMPERATURE (°C)
2631 G14
Settling to ±1LSB9th CLOCK OF3rd DATA BYTEVOUT1LSB/DIV
Settling to ±1LSB3/4 SCALE TO 1/4 SCALE STEPVCC = 5V, VFS = 4.095VRL = 2k, CL = 100pFAVERAGE OF 256 EVENTSSCL5V/DIV
4.6μsVOUT1LSB/DIV
3.9μs1/4 SCALE TO 3/4 SCALE STEPVCC = 5V, VFS = 4.095VRL = 2k, CL = 100pFAVERAGE OF 256 EVENTS2μs/DIV
2631 G15
SCL5V/DIV
9th CLOCK OF3rd DATA BYTE2μs/DIV
2631 G16
2631fb13
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LTC2631TYPICAL PERFORMANCE CHARACTERISTICS
LTC2631-10Integral Nonlinearity (INL)1.0
VCC = 5VVFS = 4.096VINTERNAL REF.1.0
TA = 25°C, unless otherwise noted.Differential Nonlinearity (DNL)VCC = 5VVFS = 4.096VINTERNAL REF.0.5
DNL (LSB)512CODE
INL (LSB)0.5
00
–0.5–0.5
–1.0
02567681023
2631 G17
–1.0
0256512CODE
7681023
2631 G18
LTC2631-8Integral Nonlinearity (INL)1.0
VCC = 3VVFS = 2.5VINTERNAL REF.Differential Nonlinearity (DNL)0.50
VCC = 3VVFS = 2.5VINTERNAL REF.0.5
DNL (LSB)128CODE
INL (LSB)0.25
00
–0.5–0.25
–1.0
064192255
2631 G19
–0.50
064128CODE
192255
2631 G20
LTC2631Load Regulation10864ΔVOUT (mV)VCC = 5V (LTC2631-H)VCC = 5V (LTC2631-L)VCC = 3V (LTC2631-L)Current Limiting0.200.150.10$VOUT(V)0.050
VCC = 5V (LTC2631-H)VCC = 5V (LTC2631-L)VCC = 3V (LTC2631-L)20–2–4–6–8–10–30
–20
–10
INTERNAL REF.CODE = MIDSCALE010IOUT (mA)
20
30
2631 G21
–0.05
–0.10–0.15–0.20
–30
–20
–10
INTERNAL REF.CODE = MIDSCALE010IOUT (mA)
20
30
2631 G22
2631fb14
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LTC2631TYPICAL PERFORMANCE CHARACTERISTICS
LTC2631Offset Error vs Temperature32OFFSET ERROR (mV)GAIN ERROR (%FSR)10–1–2–3
–50–25
0.40.30.20.10.0–0.1–0.2–0.3
0
255075100125150TEMPERATURE (°C)
2631 G23
TA = 25°C, unless otherwise noted.Gain Error vs VCCEXTERNAL REF.VREF = 2.5VGAIN ERROR (%FSR)0.40.30.20.10.0–0.1–0.2–0.3
3
3.5
4VCC (V)
4.5
5
5.5
2631 G24
Gain Error vs TemperatureEXTERNAL REF.VREF = 2.5V–0.4
2.5–0.4
–50–25
0
255075100125150TEMPERATURE (°C)
2631 G25
Large-Signal ResponseMid-Scale-Glitch Impulse9th CLOCK OF3rd DATA BYTESCL5V/DIV
VCC2V/DIV
LTC2631-H12, VCC = 5V:3.0nV-s TYPVOUT5mV/DIV
Power-On Reset GlitchLTC2631-LVOUT0.5V/DIV
ZERO-SCALELTC2631-L12, VCC = 3V:2.1nV-s TYP2μs/DIV
VOUT2mV/DIV
VFS = VCC = 5V1/4 SCALE TO 3/4 SCALE2μs/DIV
2631 G26
200μs/DIV
2631 G27
2631 G28
Headroom at Rails vs Output Current5.04.54.03.5VOUT (V)3.02.52.01.51.00.500
5V SINKING3V (LTC2631-L) SINKING1
2
3
456IOUT (mA)
7
8
9
10
VOUT0.5V/DIV
3V (LTC2631-L) SOURCING5V SOURCINGCS/LD2V/DIV
Exiting Power-Down to Mid-ScaleLTC2631-H4μs/DIV
2631 G30
2631 G29
2631fb15
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LTC2631TYPICAL PERFORMANCE CHARACTERISTICS
LTC2631Supply Current vs Logic Voltage1.21.00.8ICC (mA)ICC (mA)0.60.40.20.0
VCC = 3V(LTC2631-L)0.2
VCC = 5V0.3
VCC = 5VSWEEP SCL AND SDA BETWEEN 0V AND VCC0.5
TA = 25°C, unless otherwise noted.Supply Current vs REF_SEL VoltageSWEEP REF_SEL BETWEEN 0V AND VCC0.4
VCC = 3V(LTC2631-L)01
32
LOGIC VOLTAGE (V)
45
2631 G31
0.1
01
324
REF_SEL VOLTAGE (V)
5
2631 G32
Multiplying Bandwidth0–2–4–6dB–8–10–12
–14VCC = 5VVREF(DC) = 2V–16VREF(AC) = 0.2VP-PCODE = FULL SCALE–18
100k1k10k
FREQUENCY (Hz)
1000k
2631 G33
Noise Voltage vs Frequency500
INTERNAL REF.CODE = MIDSCALE0.1Hz to 10Hz Voltage NoiseLTC2631-L, VCC = 4V INTERNAL REF.CODE = MIDSCALENOISE VOLTAGE (nV/√Hz)400
300
LTC2631-H(VCC = 5V)10μV/DIV
200
100
LTC2631-L(VCC = 4V)0100
1k10kFREQUENCY (Hz)
100k1M
2631 G34
1s/DIV
2631 G35
2631fb16
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LTC2631PIN FUNCTIONS
CA0 (Pin 1): Chip Address Bit 0. Tie this pin to VCC, GND or leave it fl oating to select an I2C slave address for the part (see Tables 1 and 2).SCL (Pin 2): Serial Clock Input Pin. Data is shifted into the SDA pin at the rising edges of the clock. This high impedance pin requires a pull-up resistor or current source to VCC.SDA (Pin 3): Serial Data Bidirectional Pin. Data is shifted into the SDA pin and acknowledged by the SDA pin. This pin is high impedance while data is shifted in. Open-drain N-channel output during acknowledgment. SDA requires a pull-up resistor or current source to VCC.GND (Pin 4): Ground.VCC (Pin 5): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V (LTC2631-L) or 4.5V ≤ VCC ≤ 5.5V (LTC2631-H). Bypass to GND with a 0.1μF capacitor.REF (Pin 6): Reference Voltage Input or Output. When External Reference mode is selected, REF is an input (0V ≤ VREF ≤ VCC) where the voltage supplied sets the full-scale voltage. When Internal Reference is selected, the 10ppm/°C 1.25V (LTC2631-L) or 2.048V (LTC2631-H) internal reference is available at the pin. This output may be bypassed to GND with up to 10μF (0.33μF is recom-mended), and must be buffered when driving external DC load current.VOUT (Pin 7): DAC Analog Voltage Output.CA1 (Pin 8, LTC2631-Z): Chip Address Bit 1. Tie this pin oating to select an I2C slave ad-to VCC, GND or leave it fldress for the part (see Table 1).REF_SEL (Pin 8, LTC2631-M): Selects default Reference at power up. Tie to VCC to select the Internal Reference, or GND to select an External Reference. After power-up, the logic state at this pin is ignored and the reference may be changed only by software command. 2631fb17
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LTC2631BLOCK DIAGRAMS
LTC2631-ZCA1CA0VCCI2CADDRESSDECODEINTERNALREFERENCEREFSWITCHSCLI2CINTERFACESDACONTROLDECODE LOGICRESISTORDIVIDERDACREFINPUTREGISTERDACREGISTERDACVOUTGNDLTC2631-MVCCCA0I2CADDRESSDECODEINTERNALREFERENCESWITCHREF_SELREFSCLI2CINTERFACESDACONTROLDECODE LOGICRESISTORDIVIDERDACREFINPUTREGISTERDACREGISTERDACVOUTGND2631 BD2631fb18
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LTC2631TEST CIRCUITS
Test Circuits for I2C Digital I/O (See Electrical Characteristics)Test Circuit 1
Test Circuit 2
VCC100ΩCAnVIH(CAn)/VIL(CAn)RINH/RINL/RINFCAnGND2631 TC2631fb19
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TIMING DIAGRAMS
20
SDAtftLOWtrSCLtHD(STA)tHD(DAT)tHIGHS2631 F01tSU(DAT)tHD(STA)tSPtrtBUFtfSALL VOLTAGE LEVELS REFER TO VIH(MIN) AND VIL(MAX) LEVELStSU(STA)PStSU(STO)Figure 1. Serial Interface TimingSLAVE ADDRESSA167891234567891234A0WACKC3ACK5C2C1C0XXXX1ST DATA BYTE2ND DATA BYTEACK67891233RD DATA BYTEX45X6X7X8ACK92631 F02STARTSDAA6A5A4A3A2SCL12345Figure 2. Typical LTC2631 Write Transaction2631fb元器件交易网www.cecb2b.com
LTC2631OPERATION
The LTC2631 is a family of single voltage-output DACs in 8-lead ThinSOT packages. Each DAC can operate rail-to-rail using an external reference, or with its full-scale voltage set by an integrated reference. Twelve combinations of accuracy (12-, 10-, and 8-bit), power-on reset value (zero or mid-scale), and full-scale voltage (2.5V or 4.096V) are available. The LTC2631 is controlled using a 2-wire I2C interface.Power-On ResetThe LTC2631-HZ/LTC2631-LZ clear the output to zero-scale when power is fi rst applied, making system initialization consistent and repeatable.For some applications, downstream circuits are active during DAC power-up, and may be sensitive to nonzero outputs from the DAC during this time. The LTC2631 contains circuitry to reduce the power-on glitch: the analog output typically rises less than 5mV above zero-scale during power on if the power supply is ramped to 5V in 1ms or more. In general, the glitch amplitude decreases as the power supply ramp time is increased. See “Power-On Reset Glitch” in the Typical Performance Characteristics section.The LTC2631-HM/LTC2631-LM provide an alternative reset, setting the output to mid-scale when power is fi rst applied.Default reference mode selection is described in the Ref-erence Modes section.Power Supply SequencingThe voltage at REF (Pin 6) should be kept within the range – 0.3V ≤ VREF ≤ VCC + 0.3V (see Absolute Maximum Rat-ings). Particular care should be taken to observe these limits during power supply turn-on and turn-off sequences, when the voltage at VCC (Pin 5) is in transition.Transfer FunctionThe digital-to-analog transfer function is ⎛k⎞
VOUT(IDEAL)=⎜N⎟VREF
⎝2⎠
where k is the decimal equivalent of the binary DAC input code, N is the resolution, and VREF is either 2.5V (LTC2631-LM/LTC2631-LZ) or 4.096V (LTC2631-HM/LTC2631-HZ) when in Internal Reference mode, and the voltage at REF (Pin 6) when in External Reference mode.I2C Serial InterfaceThe LTC2631 communicates with a host using the stan-dard 2-wire I2C interface. The Timing Diagrams (Figures 1 and 2) show the timing relationship of the signals on the bus. The two bus lines, SDA and SCL, must be high when the bus is not in use. External pull-up resistors or current sources are required on these lines. The value of these pull-up resistors is dependent on the power supply and cations. For an I2C can be obtained from the I2C specifibus operating in the fast mode, an active pull-up will be necessary if the bus capacitance is greater than 200pF.The LTC2631 is a receive-only (slave) device. The master can write to the LTC2631. The LTC2631 does not respond to a read from the master.START (S) and STOP (P) ConditionsWhen the bus is not in use, both SCL and SDA must be high. A bus master signals the beginning of a communi-cation to a slave device by transmitting a START condition. A START condition is generated by transitioning SDA from high to low while SCL is high.When the master has fi nished communicating with the slave, it issues a STOP condition. A STOP condition is generated by transitioning SDA from low to high while SCL is high. The bus is then free for communication with another I2C device.AcknowledgeThe Acknowledge signal is used for handshaking between the master and the slave. An Acknowledge (active LOW) generated by the slave lets the master know that the latest byte of information was properly received. The Acknowledge related clock pulse is generated by the master. The master releases the SDA line (HIGH) during the Acknowledge clock pulse. The slave-receiver must pull down the SDA bus line during the Acknowledge clock pulse so that it remains a stable LOW during the HIGH period of this clock pulse. The LTC2631 responds to a write by a 2631fb21
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LTC2631OPERATION
master in this manner but does not acknowledge a read operation; in that case, SDA is retained HIGH during the period of the Acknowledge clock pulse. Chip AddressThe state of pins CA0 and CA1 (LTC2631-HZ/LTC2631-LZ) determines the slave address of the part. These pins can each be set to any one of three states: VCC, GND or fl oat. This results in nine (LTC2631-HZ/LTC2631-LZ) or three (LTC2631-HM/LTC2631-LM) selectable addresses for the part. The slave address assignments are shown in Tables 1 and 2.Table 1. Slave Address Map (LTC2631-Z)CA1GNDGNDGNDFLOATFLOATFLOATVCCVCCVCCCA0GNDFLOATVCCGNDFLOATVCCGNDFLOATVCCA60000000001A50000111111A41111000011A30000000000A20000000000A10011001101A00101010101The maximum capacitive load allowed on the CA0/CA1 address pins is 10pF, as these pins are driven during ad-dress detection to determine if they are fl oating.Write Word ProtocolThe master initiates communication with the LTC2631 with a START condition and a 7-bit slave address followed by the Write bit (W) = 0. The LTC2631 acknowledges by pulling the SDA pin low at the ninth clock if the 7-bit slave address matches the address of the part (set by CA0/CA1) or the global address. The master then transmits 3-bytes of data. The LTC2631 acknowledges each byte of data by pulling the SDA line low at the ninth clock of each data byte transmission. After receiving three complete bytes of data, the LTC2631 executes the command specifi ed in the 24-bit input word.If more than three data bytes are transmitted after a valid 7-bit slave address, the LTC2631 does not acknowledge the extra bytes of data (SDA is high during the 9th clock).The format of the three data bytes is shown in Figure 3. The fi rst byte of the input word consists of the 4-bit command, followed by four don’t-cares bits. The next two bytes contain the 16-bit data word, which consists of the 12-, 10- or 8-bit input code, MSB to LSB, followed by 4, 6 or 8 don’t-cares bits (LTC2631-12, LTC2631-10 and LTC2631-8 respectively). A typical LTC2631 write transaction is shown in Figure 4.The command bit assignments (C3-C0) are shown in Table 3. The fi rst four commands in the table consist of write and update operations. A write operation loads a 16-bit data word from the 32-bit shift register into the input register. In an update operation, the data word is copied from the input register to the DAC register and converted to an analog voltage at the DAC output. The update operation also powers up the DAC if it had been in power-down mode. The data path and registers are shown in the Block Diagram.GLOBAL ADDRESSTable 2. Slave Address Map (LTC2631-M)CA0GNDFLOATVCCGLOBAL ADDRESSA60001A50001A41111A30000A20000A10011A00101In addition to the address selected by the address pins, the part also responds to a global address. This address allows a common write to all LTC2631 parts to be accomplished using one 3-byte write transaction on the I2C bus. The global address, listed at the end of Tables 1 and 2, is a 7-bit hardwired address not selectable by CA0/CA1. If another address is required, please consult the factory.2631fb22
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LTC2631OPERATION
Write Word Protocol for LTC2631
S
SLAVE ADDRESS
W
A
1ST DATA BYTE
A
2ND DATA BYTEINPUT WORD
A3RD DATA BYTEAP
Input Word (LTC2631-12)
C3
C2
C1C0
X
X
X
X
D11D10D9
D8
D7D6D5D4D3D2D1D0XXXX
1ST DATA BYTE2ND DATA BYTE3RD DATA BYTE
Input Word (LTC2631-10)
C3
C2
C1C0
X
X
X
X
D9
D8
D7
D6
D5
D4
D3
D2D1D0
X
X
X
X
X
X
1ST DATA BYTE2ND DATA BYTE3RD DATA BYTE
Input Word (LTC2631-8)
C3
C2
C1C0
X
X
X
XD7
D6
D5
D4
D3
D2
D1
D0
XX
X
X
X
X
X
X
2631 F03
1ST DATA BYTE2ND DATA BYTE3RD DATA BYTE
Figure 3. Command and Data Input FormatTable 3. Command CodesCOMMAND*C3000000C2000111C1001011C0011001Write to Input RegisterUpdate (Power Up) DAC RegisterWrite to and Update (Power Up) DAC RegisterPower DownSelect Internal ReferenceSelect External Referenceto the REF pin will improve noise performance; 0.33μF is recommended, and up to 10μF can be driven without oscillation. This output must be buffered when driving external DC load current.Alternatively, the DAC can operate in External Reference mode using command 0111. In this mode, an input voltage supplied externally to the REF pin provides the reference (0V ≤ VREF ≤ VCC) and the supply current is reduced. External Reference mode is the power-on default for LTC2631-HM/LTC2631-LM when REF_SEL is tied low.The reference mode of LTC2631-HZ/LTC2631-LZ can be changed only by software command. The same is true for LTC2631-HM/LTC2631-LM after power-on, after which the logic state on REF_SEL is ignored.Power-Down ModeFor power-constrained applications, the LTC2631’s power-down mode can be used to reduce the supply current whenever the DAC output is not needed. When in power down, the buffer amplifi er, bias circuit, and reference circuit are disabled and draw essentially zero current. The DAC output is put into a high-impedance state, and the output pin is passively pulled to ground through a 200kΩ resistor. Input and DAC register contents are not disturbed during power down.2631fb*Command codes not shown are reserved and should not be used.Reference ModesFor applications where an accurate external reference is not available, the LTC2631 has a user-selectable, integrated reference. The LTC2631-LM/LTC2631-LZ provide a full-scale output of 2.5V. The LTC2631-HM/LTC2631-HZ provide a full-scale output of 4.096V. The internal reference can be useful in applications where the supply voltage is poorly regulated. Internal Reference mode can be selected by using command 0110, and is the power-on default for LTC2631-HZ/LTC2631-LZ, as well as for LTC2631-HM/LTC2631-LM when REF_SEL is tied high.The 10ppm/°C, 1.25V (LTC2631-LM/LTC2631-LZ) or 2.048V (LTC2631-HM/LTC2631-HZ) internal reference is available at the REF pin. Adding bypass capacitance 23
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LTC2631OPERATION
The DAC can be put into power-down mode by using command 0100. The supply current is reduced to 1.8μA maximum (C and I grades) and the REF pin becomes high impedance (typically > 1GΩ).Normal operation resumes after executing any command that includes a DAC update, as shown in Table 3. The DAC is powered up and its voltage output is updated. Normal settling is delayed while the bias, reference, and amplifi er circuits are re-enabled. When the REF pin output is bypassed to GND with 1nF or less, the power-up delay time is 20μs for settling to 12-bits. This delay increases to 200μs for 0.33μF, and 10ms for 10μF.Voltage OutputThe LTC2631’s integrated rail-to-rail amplifi er has guar-anteed load regulation when sourcing or sinking up to 10mA at 5V, and 5mA at 3V.Load regulation is a measure of the amplifi er’s ability to maintain the rated voltage accuracy over a wide range of load current. The measured change in output voltage per change in forced load current is expressed in LSB/mA.DC output impedance is equivalent to load regulation, and may be derived from it by simply calculating a change in units from LSB/mA to ohms. The amplifi er’s DC output impedance is 0.1Ω when driving a load well away from the rails.When drawing a load current from either rail, the output voltage headroom with respect to that rail is limited by the 50Ω typical channel resistance of the output devices (e.g., when sinking 1mA, the minimum output voltage is 50Ω • 1mA, or 50mV). See the graph “Headroom at Rails vs. Output Current” in the Typical Performance Charac-teristics section.The amplifi er is stable driving capacitive loads of up to 500pF.Rail-to-Rail Output ConsiderationsIn any rail-to-rail voltage-output device, the output is lim-ited to voltages within the supply range.Since the analog output of the DAC cannot go below ground, it may limit the lowest codes, as shown in Figure 5b. 2631fbSimilarly, limiting can occur near full-scale when the REF pin is tied to VCC. If VREF = VCC and the DAC full-scale error (FSE) is positive, the output for the highest codes limits at VCC, as shown in Figure 5c. No full-scale limiting can occur if VREF is less than VCC – FSE.Offset and linearity are defi ned and tested over the region of the DAC transfer function where no output limiting can occur.Board LayoutThe PC board should have separate areas for the analog and digital sections of the circuit. A single, solid ground plane should be used, with analog and digital signals carefully routed over separate areas of the plane. This keeps digital signals away from sensitive analog signals and minimizes the interaction between digital ground currents and the analog section of the ground plane. The resistance from the LTC2631 GND pin to the ground plane should be as low as possible. Resistance here will add directly to the effective DC output impedance of the device (typically 0.1Ω). Note that the LTC2631 is no more susceptible to this effect than any other parts of this type; on the contrary, it allows layout-based performance improvements to shine rather than limiting attainable performance with excessive internal resistance.Another technique for minimizing errors is to use a sepa-rate power ground return trace on another board layer. The trace should run between the point where the power supply is connected to the board and the DAC ground pin. Thus the DAC ground pin becomes the common point for analog ground, digital ground, and power ground. When the LTC2631 is sinking large currents, this current fl ows out the ground pin and directly to the power ground trace without affecting the analog ground plane voltage.It is sometimes necessary to interrupt the ground plane to confi ne digital ground currents to the digital portion of the plane. When doing this, make the gap in the plane only as long as it needs to be to serve its purpose and ensure that no traces cross over the gap.24
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OPERATION
SLAVE ADDRESSA0C3ACK89123456789123456789C3ACKACK12C2C1C0XXXXC2C1C0XXXXA07WD11D10D9D8D7D6D5D4D3D2COMMANDMS DATAD1LS DATAD0XXXXSTOPACK3456789FULL-SCALEVOLTAGEZERO-SCALEVOLTAGE2631 F04A6A5A4A3A2A1STARTSDAA6A5A4A3A2A1SCL123456VOUTX = DON’T CAREFigure 4. Typical LTC2631 Input Waveform—Programming 12-Bit DAC Output for Full-ScaleLTC263125
2631fb元器件交易网www.cecb2b.com
LTC2631OPERATION
VREF = VCCPOSITIVEFSE
VREF = VCCOUTPUTVOLTAGE
OUTPUTVOLTAGEINPUT CODE(c)0V2631 F05 OUTPUTVOLTAGE02,048INPUT CODE(a)4,0950VNEGATIVEOFFSET
INPUT CODE(b)Figure 5. Effects of Rail-to-Rail Operation on a DAC Transfer Curve (Shown for 12-Bits) (a) Overall Transfer Function (b) Effect of Negative Offset for Codes Near Zero (c) Effect of Positive Full-Scale Error for Codes Near Full-Scale2631fb26
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LTC2631PACKAGE DESCRIPTION
TS8 Package8-Lead Plastic TSOT-23(Reference LTC DWG # 05-08-1637)0.52MAX0.65REF2.90 BSC(NOTE 4)1.22 REF3.85 MAX2.62 REF1.4 MIN2.80 BSC1.50 – 1.75(NOTE 4)PIN ONE IDRECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.65 BSC0.22 – 0.36 8 PLCS (NOTE 3)0.80 – 0.900.20 BSC1.00 MAXDATUM ‘A’0.01 – 0.100.30 – 0.50 REFNOTE:
1. DIMENSIONS ARE IN MILLIMETERS2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR5. MOLD FLASH SHALL NOT EXCEED 0.254mm6. JEDEC PACKAGE REFERENCE IS MO-193
0.09 – 0.20(NOTE 3)
1.95 BSCTS8 TSOT-23 0802
2631fbInformation furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.27
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LTC2631TYPICAL APPLICATION
Programmable ±5V Output5V5V0.1μF31.7kI2C BUSCA01.7k56VCCREF8REF_SEL3SDALTC2631AVOUT72SCL-LM121CA0GND445LTC20540.1μF18M99M310M11P12P33P910V7VCCLT1991VEE4REFOUT56VOUT = ±5V
0.1μF–+20.1μF–10V2631 TA03
RELATED PARTS
PART NUMBERLTC1663LTC1669LTC2360-LT2362/LTC2365-LTC2366LTC2450/LTC2452LTC2451/LTC2453LTC2600/LTC2610/LTC2620LTC2601/LTC2611/LTC2621LTC2602/LTC2612/LTC2622LTC2604/LTC2614/LTC2624LTC2605/LTC2615/LTC2625LTC2606/LTC2616/LTC2626LTC2609/LTC2619/LTC2629LTC2630LTC2640DESCRIPTIONSingle 10-Bit VOUT DAC in SOT-23Single 10-Bit VOUT DAC in SOT-2312-Bit SAR ADCs in TSOT23-6/TSOT23-8 Packages16-Bit Single-Ended/Differential Delta Sigma ADCs16-Bit Single-Ended/Differential Delta Sigma ADCsOctal 16-/14-/12-Bit VOUT DACs in 16-Lead SSOPSingle 16-/14-/12-Bit VOUT DACs in 10-Lead DFNDual 16-/14-/12-Bit VOUT DACs in 8-Lead MSOPQuad 16-/14-/12-Bit VOUT DACs in 16-Lead SSOPOctal 16-/14-/12-Bit VOUT DACs with I2C InterfaceSingle 16-/14-/12-Bit VOUT DACs with I2C InterfaceQuad 16-/14-/12-Bit VOUT DACs with I2C InterfaceSingle 12-/10-/8-Bit VOUT DACs with 10ppm/°C Reference in SC70COMMENTSVCC = 2.7V to 5.5V, 60μA, Internal Reference, SMBus InterfaceVCC = 2.7V to 5.5V, 60μA, Internal Reference, I2C Interface100ksps/250ksps/500ksps/1Msps/3Msps Output RatesSPI Interface, Tiny DFN Packages, 60Hz Output RateI2C Interface, Tiny DFN and TSOT23-8 Packages, 60Hz Output Rate250μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, SPI Serial Interface300μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, SPI Serial Interface300μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, SPI Serial Interface250μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, SPI Serial Interface250μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, I2C Interface270μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, I2C Interface250μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output with Separate VREF Pins for Each DAC180μA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, Rail-to-Rail Output, SPI InterfaceSingle 12-/10-/8-Bit SPI VOUT DACs with 10ppm/°C 180μA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, Reference in ThinSOTSelectable External Reference Mode, Rail-to-Rail Output, SPI Interface2631fb28
Linear Technology CorporationLT 1108 REV B • PRINTED IN USA
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