Clock recovery circuit

专利名称：Clock recovery circuit发明人：OKAMOTO KOUJI申请号：US73418300申请日：20001212公开号：US6393084B2公开日：20020521

摘要：An oscillating clock frequency of a VFO (variable frequency oscillator) iscontrolled, using the results of addition of an output from a constant multiplier and anoutput from an accumulator, which is a result of accumulation of outputs from anotherconstant multiplier, based on a phase error signal by setting the output from an enable-provided latch to 0 during a frequency pull-in operation. A control signal generatingportion outputs a pulse at the Hi level as a control signal when completion of frequencypull-in is detected. The latch stores the output from the constant multiplier at the timewhen the control signal is supplied. Thus, a phase pull-in operation is started in the statewhere a latch output representing a frequency correction component is obtained. Duringthe phase pull-in operation, the VFO is controlled using the result of addition of anoutput from the multiplier, an output from the accumulator and an output from thelatch. Thus, high speed phase pull-in can be achieved, for example, in reproducing datasignal recorded in a recording medium.

申请人：MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

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