专利名称：Integrated circuits with reduced substrate
capacitance
发明人：Heemyong Park,Fariborz Assaderaghi,Jack
A. Mandelman,Ghavam G. Shahidi,Lawrence F.Wagner, Jr.
申请号：US09702314申请日：20001031公开号：US06562666B1公开日：20030513
专利附图：
摘要：Capacitance between source/drain and p-type substrate in SOI CMOS circuits is
reduced by implanting an n-type layer below the oxide layer, thereby forming a fullydepleted region that adds to the thickness of the oxide layer, while creating a junctioncapacitance region that reduces the total device to substrate capacitance.
申请人：INTERNATIONAL BUSINESS MACHINES CORPORATION
代理人：Eric W. Petraske
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