Memory embedded logic integrated circuit mounting

专利名称：Memory embedded logic integrated circuit

mounting memory circuits having differentperformances on the same chip

发明人：Kaneko, Tetsuya, Intellectual Property

Division

申请号：EP02011553.1申请日：20020524公开号：EP1349174A3公开日：20040616

专利附图：

摘要：A semiconductor integrated circuit includes a first DRAM circuit (13-1) having a

first memory cell array having a plurality of memory cells each including a first MOStransistor, and a first potential generating circuit which generates at least one potentialused to operate the plurality of memory cells in the first memory cell array, the firstDRAM circuit being formed in a semiconductor chip (11), and a second DRAM circuit (13-2)having a second memory cell array having a plurality of memory cells each including asecond MOS transistor different in characteristic from the first MOS transistor, and asecond potential generating circuit which generates at least one potential used tooperate the plurality of memory cells in the second memory cell array, the second DRAMcircuit being formed in the semiconductor chip.

申请人：Kabushiki Kaisha Toshiba

地址：1-1, Shibaura 1-chome, Minato-ku Tokyo JP

国籍：JP

代理机构：HOFFMANN - EITLE

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