本科毕业设计（外文翻译）
题 目 小型交通灯控制系统的 设计与制作 姓 名 韦 强 专 业 电子科学与技术 学 号 201031090
指导老师 洪 新 华
郑州科技学院电气工程学院 二0一四年五月二日
THE DESIGN AND MANUFACTURE OF SMALL TRAFFIC
LIGHT CONTROL SYSTEM
8-bit Microcontroller With 8K Bytes Flash AT89C52
Description
The AT89C52 is a low-power, high-performance CMOS 8-bit microcomputer with 8K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard 80C51 and 80C52 instruction set and pin out. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C52 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications.
Pin Configurations
1
Pin Description
VCC
Supply voltage. GND Ground. Port 0
Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pull-ups are required during program verification. Port 1
Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the following table. Port 1 also receives the low-order address bytes during Flash programming and verification.
2
Port 2
Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memories that use 16-bit addresses (MOVX @DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memories that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification. Port 3
Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups.
Port 3 also serves the functions of various special features of the AT89C51, as shown in the following table. Port 3 also receives some control signals for Flash programming and verification.
3
RST
Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. PSEN
Program Store Enable is the read strobe to external program memory. When the AT89C52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2
Output from the inverting oscillator amplifier. Timer 2 Registers
Control and status bits are contained in registers T2CON and T2MOD for Timer 2. The register pair (RCAP2H, RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode. Interrupt Registers
4
The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the six interrupt sources in the IP register.
5
小型交通灯控制系统的设计与制作
8位8字节闪存单片机AT89C52
功能特性描述
AT89S52是一种低功耗、高性能CMOS8位微控制器，具有8K内置可编程闪存。产品使用了Atmel公司高密度非易失性存储器技术制造，与工业80C51和80C52产品指令和引脚完全兼容。片上Flash允许程序存储器在系统可编程，亦适于常规编程器。在单芯片上，拥有灵巧的8位CPU和在系统可编程Flash，使得AT89S52为众多嵌入式控制应用系统提供高灵活、超有效的解决方案。
引脚结构
VCC : 电源 GND : 地
6
P0口：P0口是一个8位漏极开路的双向I/O口。作为输出口，每位能驱动8个TTL逻辑电平。对P0端口写“1”时，引脚用作高阻抗输入。当访问外部程序和数据存储器时，P0口也被作为低8位地址/数据复用。在这种模式下，P0具有内部上拉电阻。在flash编程时，P0口也用来接收指令字节；在程序校验时，输出指令字节。程序校验时，需要外部上拉电阻。
P1口：P1 口是一个具有内部上拉电阻的8位双向I/O 口，P1 输出缓冲器能驱动4个TTL 逻辑电平。对P1端口写“1”时，内部上拉电阻把端口拉高，此时可以作为输入口使用。作为输入使用时，被外部拉低的引脚由于内部电阻的原因，将输出电流（IIL）。此外，P1.0和P1.2分别作定时器/计数器2的外部计数输入（P1.0/T2）和时器/计数器2的触发输入（P1.1/T2EX），具体如下表所示。在flash编程和校验时，P1口接收低8位地址字节。
P2 口：P2 口是一个具有内部上拉电阻的8 位双向I/O 口，P2输出缓冲器能驱动4个TTL 逻辑电平。对P2端口写“1”时，内部上拉电阻把端口拉高，此时可以作为输入口使用。作为输入使用时，被外部拉低的引脚由于内部电阻的原因，将输出电流（IIL）。在访问外部程序存储器或用16位地址读取外部数据存储器（例如执行MOVX @DPTR）时，P2口送出高八位地址。在这种应用中，P2口使用很强的内部上拉发送1。在使用8位地址（如MOVX @RI）访问外部数据存储器时，P2口输出P2锁存器的内容。在flash编程和校验时，P2口也接收高8位地址字节和一些控制信号。 P3 口：P3口是一个具有内部上拉电阻的8位双向I/O 口，P2输出缓冲器能驱动4个TTL 逻辑电平。对P3端口写“1”时，内部上拉电阻把端口拉高，此时可以作为输入口使用。作为输入使用时，被外部拉低的引脚由于内部电阻的原因，将输出电流（IIL）。P3口亦作为AT89S52特殊功能（第二功能）使用，如下表所示。在flash
7
编程和校验时，P3口也接收一些控制信号。
RST: 复位输入。晶振工作时，RST脚持续2个机器周期高电平将使单片机复位。看门狗计时完成后，RST脚输出96个晶振周期的高电平。特殊寄存器AUXR(地址8EH)上的DISRTO位可以使此功能无效。DISRTO默认状态下，复位高电平有效。
PSEN :外部程序存储器选通信号（PSEN ）是外部程序存储器选通信号。 当 AT89S52从外部程序存储器执行外部代码时，PSEN 在每个机器周期被激活两次，而在访问外部数据存储器时，PSEN 将不被激活。
EA /VPP:访问外部程序存储器控制信号。为使能从0000H 到FFFFH的外部程序存储器读取指令，EA 必须接GND。为了执行内部程序指令，EA 应该接VCC。 在flash编程期间，EA 也接收12伏VPP电压。
XTAL1:振荡器反相放大器和内部时钟发生电路的输入端。 XTAL2:振荡器反相放大器的输出端。
定时/计数器2
定时/计数器2的控制和状态位位于T2CON和T2MOD。寄存器对（RCAO2H、RCAP2L）是定时器2在16位捕获方式或16位自动重装载方式下的捕获/自动重装载寄存器。
8
中断寄存器
所有单独的中断允许位都存在于中断允许寄存器IE中。中断优先级寄存器IP可以为六个中断源设置两个中断优先级。
9
因篇幅问题不能全部显示，请点此查看更多更全内容