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TH7888AVRHN资料

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Features

•1024 x 1024 Pixels with Memory Zone•Up to 30 Images/Second

•Built-in Antiblooming Device Providing an Electric Shutter Function•Pixel: 14 µm x 14 µm

•Image Zone: 14.34 x 14.34 mm2•Two Outputs at 20 MHz Each•Readout Through 1 or 2 Outputs•Possible Binning 2 x 2

•Optical Shield Against Parasitic Reflexions and Stray Light•

A/R Window in 400 - 700 nm Bandwidth

Description

The TH7888A is particularly designed for high data rate applications (up to 30 pic-tures/second in 1024 x 1024 progressive scan format) in the medical and industrialfields. This area array image sensor consists of a 1024 x 1024 pixels (14 µm x 14 µm)image zone associated with a memory zone (masked with an optical shield). Toincrease the data rate, two separate outputs are provided, which can be used for par-allel readout (the readout frequency is up to 20 MHz/output, leading to a total readoutfrequency of 40 MHz). These two outputs allow three readout modes (single or dualport). The TH7888A is designed with an antiblooming structure which provides anelectronic shutter capability. Moreover, the 2 x 2 binning mode is available on this sen-sor, providing an image size of 512 x 512 pixels with 28 µm x 28 µm pixels. TheTH7888A package is sealed with a specific anti-reflective window optimized in the 400- 700 nm spectrum bandwidth on the sealed version.

Area Array CCD Image Sensor (1024 x 1024 Pixels with Antiblooming)TH7888ARev. 1999A–IMAGE–09/031

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Figure 1. TH7888A General Sensor Organization

ΦP1,2,3,4ΦM1,2,3,4ΦAVA1024 x 1024Image Area1024 x 1024Memory AreaVDRΦMVDRΦRVDD1VOS1VS1Bi-directional Serial RegisterVGSΦRVDD2VOS2VS2ΦL1-6 VGSFunctional Overview

Extra dark lines are provided for use as dark references or for smearing digital correc-tion.

Extra dark pixels are provided for dark line reference clamping. Each frame consists of1056 video lines:•••••••

1 dummy line

12 useful dark reference lines (with optical shield)3 isolation lines1024 useful lines3 isolation lines

12 dark reference lines (with optical shield)1 dummy line

Each video line is made up of 546 or 1058 elements, depending on the readout mode(single or dual port mode):•••••

12 inactive prescan elements1 isolation prescan element

16 useful dark references (with optical shield)5 isolation elements

512 or 1024 useful video pixels

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TH7888A

Pin Description

Figure 2. Pin Overview

AAΦP4ΦP2VSSΦP3ΦP1VSSVAΦM4ΦM2VSSΦAΦM3ΦM1ΦMNC NC NCY NC NC NCBVS1VOS2VS2VDPVSSVSSΦRΦL4ΦL1ΦL5AVOS1VDD1VDD2VDRVGSVSSVSSΦL3ΦL2ΦL61098765Top View4321A1 IndexTable 1. Pin Description

Pin NumberY9AA9Y10AA10Y5AA5Y6AA6Y4B2A2A3B3B1A1A9A8B10B8B7A6A10B9B4

SymbolΦP1ΦP2ΦP3ΦP4ΦM1ΦM2ΦM3ΦM4ΦMΦL1ΦL2ΦL3ΦL4ΦL5ΦL6VDD1VDD2VS1VS2VDPVGSVOS1VOS2ΦR

Output amplifier drain supplyReadout register clocksMemory to register clockMemory zone clocksImage zone clocksDesignation

Output amplifier source supplyProtection drain biasRegister output gate biasVideo outputsReset clock

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Table 1. Pin Description (Continued)

Pin NumberY7A7AA7

A4, A5, B5, B6Y8, AA4, AA8

SymbolΦAVDRVAVSSVSS

Designation

Antiblooming gate clockReset bias

Antiblooming diode biasSubstrate bias

Geometrical Characteristics

Figure 3. Pixel Layout

ΦAVAΦAAΦ P1ΦP2ΦP3ΦP4ΦP1A'Aperture 10 µm14 µmΦAΦAVA14 µmFigure 4. AA Cross Section

ΦP1ΦP2ΦP3ΦP4ΦP114 µmTransfer DirectionPotential ProfileDuring Integration TimeSignal Chargefor One Pixel4

TH7888A

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TH7888A

Absolute Maximum Ratings*

Storage Temperature.....................................-55°C to +150°COperating Temperature....................................-40°C to +85°CThermal Cycling..........................................................15°C/mnMaximum Applied Voltages:

• Pins: Y9, AA9, Y10, AA10, Y5, AA5, Y6,

AA6, Y4, B2, A2, A3, B3, B1, A1, B4, A6...........-0.3 V to 15 V• Pins: A9, A8, B10, B8, B7, A7, AA7..............-0.3 V to 15.5 V• Pin: Y7..............................................................-0.3 V to 12 V• Pins: A4, A5, B5, B6, Y8, AA4, AA8...................0 V (ground)

*NOTICE:

*Stresses above those listed under absolute maximum ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum rat-ings for extended periods may affect device reli-ability. Operating range defines the limits within which functionality is guaranteed. Electrical limits of applied signals are given in the operating con-ditions section.

Operating Precautions

Shorting the video outputs to any pin, even temporarily, can permanently damage theon-chip output amplifier.

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Operating Conditions

Table 2. DC Characteristics

Value

Parameter

Output amplifier drain supplyProtection drain biasReset bias

Antiblooming diode biasRegister output gate biasOutput amplifier source supplyGround(1)Notes:

SymbolVDD1, VDD2

VDPVDRVAVGSVS1(2), VS2VSS(2)

Min14.514.514.514.52.2

Typ151515152.500

Max15.515.515.515.52.8

UnitVVVVVVV

1.Ground: note that the package metal back is grounded.

2.In dynamic mode, to avoid possible damage to the device, the addition of a Schottky diode is recommended (for example;

diode reference BAR 43S) between VS1 and VSS ground in order to increase the potential on VS1, thus avoiding any directmode diode current during clock transitions.

Readout Mode

The serial readout register is operated in a two-phase transfer mode. However, thereare 6 separate command electrodes that should be connected differently, depending onthe required readout mode. The following table gives the connections to be made foreach mode.

Table 3. Readout Modes

Readout Modes Drive Clocks (Signals)ΦL1ΦL2

1 Output, VOS 1Pins B2, B3, B1Pins A2, A3, A1

1 Output, VOS2(Mirror Effect)Pins B2, A3, A1 Pins A2, B3, B1

2 Outputs (Parallel)Pins B2, B3, A1Pins A2, A3, B1

Table 4. Timing Parameters

Definition

Vertical transfer periodVertical transfer subdivisionRise timeFall time

Readout register clock transition timeReset clock transition time

Delay between output reset signal and reset clock

SymbolTVTOtrtft1t2td

CommentsNominal value = 800 nm

Tv = 8 x To

For vertical transfer clocks (between 10% and 90% of the transition time)

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TH7888A

Timing Diagrams

The following diagrams describe the 20 MHz readout frequency and 1.25 MHz verticaltransfer frequency.

Figure 5. Frame Timing Diagram

Integration Image # i + 1Image ReadoutMemory Cleaning PeriodFast Image to Memory TransferΦ AΦ P1Φ P2Φ P3Φ P41210561056 PulsesΦ M = Φ M1Φ M2Φ M3Φ M4121056Φ L1Φ L2Φ RSee Figure 6See Figure 7Figure 6. Line Timing Diagram

7ToΦ M = Φ M15ToΦ M25ToΦ M33To3ToΦ M43ToSee Figure 9100 ns Min3To100 ns MinΦ L1Φ L2Φ RVos1 (Vos2)112131058 (or 546) Min112Note 1Note 2Note 3Note 1Notes:

1.12 pre-scan elements

2.1 isolation element, 16 dark reference pixels, 5 isolation elements

3.1024 useful video pixels (single output readout mode), 512 useful video pixels (dual output readout mode)

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Figure 7. Vertical Transfer During Image to Memory Zone Transfer

20 ns < Tf < To100 ns Min100 ns Min20 ns < Tr < ToΦA121056ΦP1ΦP2ΦP3ΦP4ΦM1 = ΦM2ΦM2ΦM3ΦM4See Figure 8Figure 8. Transfer Period from Image Zone to Memory Zone (ΦP and ΦM for 1.25 Vertical Transfer FrequencyFV = 1: Tv)

Tv = 800 ns tr5 Totf3 To25 ns < Tr < To/325 ns < Tf < To/35 ToTo = 100 nsΦP1 = ΦM1ΦP2 = ΦM2ΦP3 = ΦM33 To5 ToΦP4 = ΦM4To = Tv /83 ToNote:

Tr = Rise timeTf = Fall time

To = Vertical transfer time subdivisionTv = Vertical transfer period.

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Figure 9. Output Diagram for Readout Register and Reset Clock 20 MHz Applications

Crossover of Complementary Clocks (ΦL1, ΦL2). Between 30% and 70% of Maximum Amplitude.

50 ns16 ns Min16 ns MinΦL1t1t1ΦL212 ns MinΦRt2t2tdVOS(1,2)SignalLeveltdReset FeedthroughNote:

t1 = 7 ns typicalt2 = 5 ns typical

td = 8 ns typical delay time

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TH7888A

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Binning Mode Operation

In binning mode operation, the image is composed of 512 x 512 pixels (28 µm x 28 µmeach).

Figure 10. Summation in the Readout Register of Two Adjacent Lines

15 T0Φ M1Φ M2Φ M3Φ M45 T03 T05 T05 T05 T03 T03 T03 T03 T03 T03 T05 T05 T0Φ M = Φ M1100 ns Min100 ns MinΦ L1Φ L2Note:

To view fall and rise times see Figure 8 on page 8

Figure 11. Summation of Two Adjacent Pixels

Φ L1Φ L2Output Reset FrequencyDivided by 2Φ RVOS(1,2)Pixel iUseful SignalPixel i + pixel i+110

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TH7888A

Exposure Time Reduction

The TH7888A provides an exposure time control (electronic shutter) function.

The exposure time reduction is achieved by pulsing all the ΦPi gates to 0 V to continu-ously remove all the photogenerated electrons through antiblooming drain VA.Figure 12. Timing Diagram for Electronic Shutter

Frame Period2 µsΦ AΦ P11 µsΦ P2Φ P3Φ P4TransferObturationIntegrationNote:To view fall and rise times see Figure 6 on page 7

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Table 5. Drive Clock CharacteristicsValueParameterImage zone clocksHigh levelLow levelMemory zone clocksHigh levelLow levelMemory register clocksHigh levelLow levelAntiblooming gateHigh level (integration)Low level (transfer)Reset gateHigh levelLow levelReadout register clocksHigh levelLow levelSymbolMin7.50Typ80.580.590.540.512290.5Max8.50.88.50.89.50.870.81339.50.8UnitVVVVVVVVVVVVRemarksTypical input capacitance15 nFSee Figure 12Typical input capacitance15.5 nFSee Figure 12Typical input capacitance10 pFTypical input capacitance14 nFSee Figure 12 and Figure 14Typical input capacitance10 pFΦP1, 1, 3, 4ΦM1, 2, 3, 47.50ΦM8.50ΦA30ΦR100ΦL1, 28.50Φ1L8 pFΦ2L40 pF40 pFMaximum readout register frequencyMaximum image zone to memory zone Transfer frequencyFHFV201.7––––MHzMHzSee Figure 9See Figure 1412

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TH7888A

Figure 13. Drive Clocks Capacitance Network

ΦP23.3 nF2.3 nFΦP20.7 nF0.5 nFVA0.5 nFΦP13.3 nFΦA2.3 nFΦP32.8 nFSubstrateΦP10.7 nFΦP3ΦP43.4 nFΦP4ΦP14.4 nFΦP22.2 nF4.4 nF2.2 nF4.4 nF4.4 nF3.4 nFΦP4ΦP33.9 nFΦM14.4 nFΦM23.2 nF4.4 nF3.2 nF4.4 nF4.4 nF3.9 nFΦM4ΦM3Table 6. Static and Dynamic Electrical Characteristics

Value

Parameter

Output amplifier supply currentOutput impedanceDC output level

Output conversion factor

SymbolIDDZSVREFCVF

5.5200Min

Typ10225116

6.5Max15250

UnitmAΩVµV/e-Remarksper amplifier

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Electro-optical Performance

•General conditions:

Temp = 25°C (package temperature)

Light source: 2854 K with 2 mm BG38 filter (unless specified) + F/3.5 opticalaperture.

30 images per second mode (Ti = 33 ms) under typical operating conditions

••

Readout mode: 2 outputs

Values exclude dummy elements and blemishes

Table 7. Performance Description and Values

Value

Parameter

Output register saturation levelPixel saturation level

Pixel saturation charge (electron per pixel)Responsivity at 640 nm

Responsivity with BG38 filterQuantum efficiency at 640 nmPhoto response non uniformity (1σ)Dark signal non uniformity (1σ)Average dark signal

SymbolVSAT regVSATQSATRQEPRNUDSNUVDS

Min–1.6––3–––––

Temporal RMS noise in darkness (last line)Dynamic range

Horizontal modulation transfer function at 500 nm

Vertical charge transfer inefficiency (per stage)

Horizontal charge transfer inefficiency (per stage)Notes:

VNDMTFVCTIHCTI

–––––

Typ2.61.93206.54150.40.28242008070––

Max–3––––1.70.435.6–––2.5.10-55.10-5

UnitVVke-V/(µJ/cm2)V/(µJ/cm2)

%%VosmVmVmVµVdB%––

(2)(3)(4)(5)(6)(7)(1)

Remarks

See Figure 17

(8)

(9)

1.Pixel saturation (full well) as a function of vertical transfer frequency (see Figure 14 on page 15) and antiblooming adjust-ment (see Figure 15 on page 15).

2.After substraction of dark signal slope due to memory readout time.3.First line level referenced from inactive prescan elements (12 samples).4.Last line level referenced from inactive prescan elements (12 samples).

5.Measured with Correlated Double Sampling (CDS) including 160 µV readout noise and dark current noise in general test

conditions.

6.Saturation to RMS noise in darkness ratio.7.At Nyquist frequency.

8.VSAT/2 measurement and 417 kHz vertical transfer frequency.9.VSAT/2 measurement and 10 MHz horizontal transfer frequency.

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TH7888A

Figure 14. Saturation Level by Full Well with Antiblooming Off (ΦA High = 0 V) Versus the Vertical Transfer Frequency

2 )V1.8 ( egatloV 1.6 noitarutaS1.4 1.2 20070012001700Vertical Transfer Frequency (kHz)Figure 15. Saturation Level Limitation by the Antiblooming Effect on the Pixel (Typical Operating Conditions)

InefficientAntibloomingEfficientAntiblooming)V( egatloV noitarutaS tuptuOInefficientAntiblooming ΦA High Level Clock (V)1999A–IMAGE–09/03

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Figure 16. Smearing Effect

50Smearing/Vsat(%)4030201000246100 x ESAT10 x ESAT810% of Overilluminated Zone (Height)NESAT = number of times ESAT

TVVSMEARING

-----------------------------=NESAT×-----×H

TIVSAT

with ESAT = VSAT/responsivity

(typical illumination conditions)••

Ti = integration time

Tv = image to memory transfer time

Vertical SmearingOverilluminationaVsatHbSmearing Levela,b Signal Line16

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TH7888A

Figure 17. Spectral Response with A/R Window (Typical Case) 1086Responsivity V/(µJ/cm²)420350400450500550600650700750800850900950100010501100Wavelength (nm)Image Quality Grade

BlemishClustersColumns

General Conditions

Maximum area of 2 x 2 defective pixels.Less than 7 contiguous defects in a column.More than 7 contiguous defects in a column.

Room Temperature...........................................................25°C Frequency

30 images/s(under typical operating conditions)

Considered image zone........................................1024 x 1024Light Source

2854K with BG38 filter + F/3.5 optical aperture

At Vos = 0.7 Vsat

Type

Blemishes/clustersColumns

Whiteα > 20% Vosα > 10% VosBlack|α| > 30% Vos|α| > 10% VosIn Darkness

Blemishes/clustersColumns

α > 10 mV (*)α > 5 mV (*)

(*) reference is Vo: average darkness signal

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Number of Defects

Total pixel numbers affected by blemishes and clusters.....100Maximum number of clusters................................................10Maximum number of columns.................................................5

α: amplitude of video signal of defect with respect to mean output voltage VosOrdering Codes

TH7888AVRHRB: sealed versionTH7888AVRHN: unsealed version

Figure 18. Ordering Information Key

1TH788A234567891011Technological VariantsTemperature Range V: -40°C to +85°CPackage Families R: Pin Grid Array (PGA)Image Grade H: HighCustomer SpecificationQuality Assurance Level Standard ScreeningNothing B = Mechanical MaskPackage Variants N: Non-sealed Window R: Anti-reflective Window18

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TH7888A

Package Outline

Figure 19. Package Drawing for 40-lead PGA

26.50 ±0.3Pin No. = A1 Index0,734 ± 0,152.0 ±0.60.3 ± 0.16.90 ± 0.2017.25 ± 0.202.31 ± 0.302.19 ± 0.258YΦ3.04+-0.040.5XNotes:

1.

2.3.4.5.6.7.8.9.All values are in mm.

Black alumina 40-lead PGA package

Black optical mask (only on sealed version)

400 nm – 700 nm AR coated window (R < 1% per side). Only on sealed versionMetal back, (CuW – copper tungsten) gold plated. Electrically grounded (VSS)Optical center

First useful pixel (readout through Vos1)Mechanical reference

Photosensitive area dimensions 14,392(X) x 14,358(Y)

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ParameterZtopZbottom

Mechanical Distance2.82 ± 0.311.68 ± 0.15

Optical Distance2.31 ± 0.302.19 ± 0.25

Unitmmmm

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Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warrantywhich is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errorswhich may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and doesnot make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are grantedby the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as criticalcomponents in life support devices or systems.

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