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24AA014H/24LC014H

1K I2C™ Serial EEPROM with Half-Array Write-Protect

Device Selection Table

Part Number24AA014H24LC014H

VCC Range1.7V-5.5V2.5V-5.5V

Max. Clock400kHz(1)1 MHz

Temp. RangeII, E

Description:

The Microchip Technology Inc. 24AA014H/24LC014His a 1Kbit Serial Electrically Erasable PROM withoperation down to 1.7V. The device is organized as asingle block of 128 x8-bit memory with a 2-wire serialinterface. Low-current design permits operation withmaximum standby and active currents of only 1 μA and400 μA, respectively. The device has a page writecapability for up to 16 bytes of data. Functional addresslines allow the connection of up to eight 24AA014H/24LC014H devices on the same bus for up to 8Kbits ofcontiguous EEPROM memory. The device is availablein the standard 8-pin PDIP, 8-pin SOIC (150 mil),TSSOP, 2x3 TDFN and MSOP packages.

Note1:100 kHz for VCC < 1.8V

Features:

•Single-Supply with Operation down to 1.7V•Low-Power CMOS Technology:-400 μA active current, maximum

-1 μA standby current, maximum (I-temp)•Organized as a Single Block of 128 Bytes (128 x 8)

•2-Wire Serial Interface Bus, I2C™ Compatible•Schmitt Trigger Inputs for Noise Suppression

•Output Slope Control to Eliminate Ground Bounce•100 kHz and 400 kHz Compatibility•1 MHz Compatibility (LC)

•Page Write Buffer for up to 16 Bytes

•Self-Timed Write Cycle (including Auto-Erase)•Hardware Write Protection for Half Array (40h-7Fh)

•Address Lines Allow up to Eight Devices on Bus•1 Million Erase/Write Cycles•ESD Protection > 4,000V•Data Retention > 200 Years

•Factory Programming (QTP) Available•Pb-Free and RoHS Compliant

•8-pin PDIP, SOIC, TSSOP, TDFN and MSOP Packages

•Available for Extended Temperature Ranges:-Industrial (I):-Automotive (E):

-40°C to-40°C to

+85°C+125°C

Package Types

PDIP, MSOP

A0A1A2VSS

1234

8765

VCCWPSCL

A0A1A2

SOIC, TSSOP1234

8765

VCCWPSCLSDA

SDAVSS

TDFN

A01A12A23VSS4

8VCC7WP6SCL5SDA

Block Diagram

A0 A1 A2

HV Generator

I/OControl Logic

MemoryControl Logic

XDEC

EEPROM Array

SDASCLVCCVSS

Circuitry

YDEC

Write-Protect

Sense Amp.R/W Control

Preliminary

DS22077B-page 1

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24AA014H/24LC014H

1.0

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings (†)

VCC.............................................................................................................................................................................6.5VAll inputs and outputs w.r.t. VSS.........................................................................................................-0.6V to VCC +1.0VStorage temperature...............................................................................................................................-65°C to +150°CAmbient temperature with power applied................................................................................................-40°C to +125°CESD protection on all pins......................................................................................................................................................≥ 4 kV† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to thedevice. This is a stress rating only and functional operation of the device at those or any other conditions above thoseindicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions forextended periods may affect device reliability.

TABLE 1-1:DC CHARACTERISTICS

Electrical Characteristics:Industrial (I):VCC = +1.7V to 5.5VAutomotive (E):VCC = +2.5V to 5.5VSymbolVIHVILVHYSVOLILIILOCIN, COUTICC ReadICC WriteICCS

Min.0.7 VCC

—0.05 VCC

———————

Max.—0.3 VCC

—0.40±1±11040031

UnitsVVVVμΑμApFμAmAμA

(Note1)

IOL = 3.0 mA, VCC = 4.5VIOL = 2.1 mA, VCC = 2.5VVIN = VSS or VCC, WP = VssVOUT = VSS or VCCVCC = 5.0V (Note1)TA = 25°C, f = 1 MHzVCC = 5.5V, SCL = 400 kHzVCC = 5.5V

VCC = 5.5V, SDA = SCL = VCC WP = VSS, A0, A1, A2 = VSSTA = -40°C to +85°CTA = -40°C to +125°C

Conditions

All parameters apply across the specified operating ranges unless otherwise noted.

Parameter

SCL and SDA pins:High-level input voltageLow-level input voltage

Hysteresis of Schmitt Trigger inputsLow-level output voltageInput leakage currentOutput leakage current

Pin capacitance (all inputs/outputs)Operating currentStandby current

Note1:This parameter is periodically sampled and not 100% tested.

DS22077B-page 2

Preliminary

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24AA014H/24LC014H

TABLE 1-2:

AC CHARACTERISTICS

Electrical Characteristics:Industrial (I):VCC = +1.7V to 5.5VAutomotive (E):VCC = +2.5V to 5.5V

Characteristic

Clock frequency

Min.—

——400060050047001300500——————400060025047006002500250100100400060025040006006004700600600———130047004700——1M

Max.1004001000——————10003003001000300300———————————————————3500900400———505—

UnitskHz

TA = -40°C to +85°CTA = -40°C to +125°CConditions

1.7V ≤ VCC < 1.8V1.8V ≤ VCC ≤ 5.5V

2.5V ≤ VCC ≤ 5.5V (24LC014H)1.7V ≤ VCC < 1.8V1.8V ≤ VCC ≤ 5.5V

2.5V ≤ VCC ≤ 5.5V (24LC014H)(Note2)

1.7V ≤ VCC < 1.8V1.8V ≤ VCC ≤ 5.5V

2.5V ≤ VCC ≤ 5.5V (24LC014H)1.7V ≤ VCC < 1.8V1.8V ≤ VCC ≤ 5.5V

2.5V ≤ VCC ≤ 5.5V (24LC014H)24AA014H

(Note1 and Note3)—

25°C, VCC = 5.5V, Block mode (Note4)

AC CHARACTERISTICSParam.No.1

SymbolFCLK

2THIGHClock high timens

3TLOWClock low timens

4TRSDA and SCL rise time (Note1)ns

5TFSDA and SCL fall time (Note1)ns

6THD:STAStart condition hold timens

7TSU:STAStart condition setup timens

THD:DATTSU:DAT

Data input hold timeData input setup time

nsns

10TSU:STOStop condition setup timens

11TSU:WPWP setup timens

12THD:WPWP hold timens

13TAAOutput valid from clock (Note2)ns

14TBUF

Bus free time: Time the bus must be free before a new transmission can start

Input filter spike suppression(SDA and SCL pins)

Write cycle time (byte or page)Endurance

161718

TSPTWC—

nsmscycles

Note1:Not 100% tested. CB = total capacitance of one bus line in pF.

2:As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum

300ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

3:The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved noise spike

suppression. This eliminates the need for a TI specification for standard operation.

4:This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please

consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com.

Preliminary

DS22077B-page 3

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24AA014H/24LC014H

FIGURE 1-1:

BUS TIMING DATA

SCLSDAIn

891013

SDAOut

(protected)(unprotected)14

WP1112DS22077B-page 4

Preliminary

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24AA014H/24LC014H

2.0

PIN DESCRIPTIONS

The descriptions of the pins are listed in Table2-1.

TABLE 2-1:

NameA0A1A2VSSSDASCLWPVCC

PIN FUNCTION TABLE

8-pinPDIP12345678

8-pinSOIC12345678

8-pin TSSOP12345678

8-pin MSOP12345678

8-pinTDFN12345678

Function

User Configurable Chip SelectUser Configurable Chip SelectUser Configurable Chip SelectGroundSerial DataSerial ClockWrite-Protect Input+1.7V to 5.5V (24AA014H)+2.5V to 5.5V (24LC014H)

2.1SDA Serial Data2.4WP

This is a bidirectional pin used to transfer addressesand data into and out of the device. It is an open drainterminal. Therefore, the SDA bus requires a pull-upresistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for400kHz).

For normal data transfer SDA is allowed to change onlyduring SCL low. Changes during SCL high arereserved for indicating the Start and Stop conditions.

WP is the hardware write-protect pin. It must be tied toVCC or VSS. If tied to VCC, the hardware write protectionis enabled and will protect half of the array (40h-7Fh).If the WP pin is tied to VSS the hardware writeprotection is disabled.

2.5Noise Protection

2.2SCL Serial Clock

The 24AA014H/24LC014H employs a VCC thresholddetector circuit that disables the internal erase/writelogic if the VCC is below 1.5 volts at nominal conditions.The SCL and SDA inputs have Schmitt Trigger andfilter circuits that suppress noise spikes to assureproper device operation even on a noisy bus.

The SCL input is used to synchronize the data transferto and from the device.

2.3A0, A1, A2

The A0, A1 and A2 inputs are used by the 24AA014H/24LC014H for multiple device operations. The levelson these inputs are compared with the correspondingbits in the slave address. The chip is selected if thecompare is true.

Up to eight 24AA014H/24LC014H devices may beconnected to the same bus by using different ChipSelect bit combinations. These inputs must beconnected to either VCC or VSS.

In most applications, the chip address inputs A0, A1and A2 are hard-wired to logic ‘0’ or logic ‘1’. Forapplications in which these pins are controlled by amicrocontroller or other programmable device, the chipaddress pins must be driven to logic ‘0’ or logic ‘1’before normal device operation can proceed.

Preliminary

DS22077B-page 5

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24AA014H/24LC014H

3.0

FUNCTIONAL DESCRIPTION

4.4

Data Valid (D)

The 24AA014H/24LC014H supports a bidirectional,2-wire bus and data transmission protocol. A devicethat sends data onto the bus is defined as transmitter,and a device receiving data as receiver. The bus hasto be controlled by a master device that generates theSerial Clock (SCL), controls the bus access and gen-erates the Start and Stop conditions while the24AA014H/24LC014H works as slave. Both masterand slave can operate as transmitter or receiver, butthe master device determines which mode isactivated.

The state of the data line represents valid data when,after a Start condition, the data line is stable for theduration of the high period of the clock signal.The data on the line must be changed during the lowperiod of the clock signal. There is one bit of data perclock pulse.

Each data transfer is initiated with a Start condition andterminated with a Stop condition. The number of thedata bytes transferred between the Start and Stopconditions is determined by the master device and is,theoretically, unlimited, though only the last sixteen willbe stored when doing a write operation. When anoverwrite does occur, it will replace data in a first-infirst-out fashion.

4.0BUS CHARACTERISTICS

The following bus protocol has been defined:•Data transfer may be initiated only when the bus is not busy.

•During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop condition.Accordingly, the following bus conditions have beendefined (Figure4-1).

4.5Acknowledge

Each receiving device, when addressed, is required togenerate an acknowledge after the reception of eachbyte. The master device must generate an extra clockpulse which is associated with this Acknowledge bit.Note:

The 24AA014H/24LC014H does not gen-erate any Acknowledge bits if an internalprogramming cycle is in progress.

4.1Bus Not Busy (A)

Both data and clock lines remain high.

4.2Start Data Transfer (B)

A high-to-low transition of the SDA line while the clock(SCL) is high determines a Start condition. Allcommands must be preceded by a Start condition.

4.3Stop Data Transfer (C)

The device that acknowledges has to pull down theSDA line during the Acknowledge clock pulse in such away that the SDA line is stable low during the highperiod of the acknowledge-related clock pulse. Ofcourse, setup and hold times must be taken intoaccount. A master must signal an end of data to theslave by not generating an Acknowledge bit on the lastbyte that has been clocked out of the slave. In this case,the slave must leave the data line high to enable themaster to generate the Stop condition (Figure4-2).

A low-to-high transition of the SDA line while the clock(SCL) is high determines a Stop condition. Alloperations must be ended with a Stop condition.

FIGURE 4-1:SCL(A)(B)DATA TRANSFER SEQUENCE ON THE SERIAL BUS CHARACTERISTICS(C)(D)(C)(A)SDAStartConditionAddress orAcknowledgeValidDataAllowedto ChangeStopConditionDS22077B-page 6

Preliminary

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24AA014H/24LC014H

FIGURE 4-2:ACKNOWLEDGE TIMINGAcknowledgeBitSCL123456789123SDAData from transmitterTransmitter must release the SDA line at this point allowingthe Receiver to pull the SDA line low to acknowledge theprevious eight bits of data.Data from transmitterReceiver must release the SDA line at thispoint so the Transmitter can continuesending data.© 2008 Microchip Technology Inc.

Preliminary

DS22077B-page 7

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24AA014H/24LC014H

5.0

DEVICE ADDRESSING

FIGURE 5-1:

CONTROL BYTE FORMAT

Read/Write BitChip Select

Bits0

A0R/WACK

A control byte is the first byte received following theStart condition from the master device (Figure5-1).The control byte consists of a four-bit control code; forthe 24AA014H/24LC014H this is set as ‘1010’ binaryfor read and write operations. The next three bits of thecontrol byte are the Chip Select bits (A2, A1, A0). TheChip Select bits allow the use of up to eight 24AA014H/24LC014H devices on the same bus and are used toselect which device is accessed. The Chip Select bitsin the control byte must correspond to the logic levelson the corresponding A2, A1 and A0 pins for the deviceto respond. These bits are in effect the three MostSignificant bits of the word address.

The last bit of the control byte defines the operation tobe performed. When set to a ‘1’, a read operation isselected. When set to a ‘0’, a write operation isselected. Following the Start condition, the 24AA014H/24LC014H monitors the SDA bus, checking the controlbyte being transmitted. Upon receiving a ‘1010’ codeand appropriate Chip Select bits, the slave deviceoutputs an Acknowledge signal on the SDA line.Depending on the state of the R/W bit, the 24AA014H/24LC014H will select a read or write operation.

Control Code

Slave Address

Start Bit

Acknowledge Bit

5.1

Contiguous Addressing Across Multiple Devices

The Chip Select bits A2, A1 and A0 can be used toexpand the contiguous address space for up to 8K bitsby adding up to eight 24AA014H/24LC014H devices onthe same bus. In this case, software can use A0 of thecontrol byte as address bit A8, A1 as address bit A9,and A2 as address bit A10. It is not possible tosequentially read across device boundaries.

DS22077B-page 8

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24AA014H/24LC014H

6.0

6.1

WRITE OPERATIONS

Byte Write

Following the Start signal from the master, the devicecode(4 bits), the Chip Select bits (3 bits) and theR/Wbit (which is a logic low) are placed onto the bus by themaster transmitter. The device will acknowledge thiscontrol byte during the ninth clock pulse. The next bytetransmitted by the master is the word address and willbe written into the Address Pointer of the 24AA014H/24LC014H. After receiving another Acknowledgesignal from the 24AA014H/24LC014H, the masterdevice will transmit the data word to be written into theaddressed memory location. The 24AA014H/24LC014H acknowledges again and the mastergenerates a Stop condition. This initiates the internalwrite cycle and the 24AA014H/24LC014H will notgenerate Acknowledge signals during this time(Figure6-1). If an attempt is made to write to theprotected portion of the array when the hardware writeprotection has been enabled, the device willacknowledge the command, but no data will be written.The write cycle time must be observed even if writeprotection is enabled.

The higher order four bits of the word address remainconstant. If the master should transmit more than 16bytes prior to generating the Stop condition, theaddress counter will roll over and the previouslyreceived data will be overwritten. As with the byte writeoperation, once the Stop condition is received, aninternal write cycle will begin (Figure6-2). If an attemptis made to write to the protected portion of the arraywhen the hardware write protection has been enabled,the device will acknowledge the command, but no datawill be written. The write cycle time must be observedeven if write protection is enabled.Note:

Page write operations are limited to writingbytes within a single physical page,regardless of the number of bytesactually being written. Physical pageboundaries start at addresses that areinteger multiples of the page buffer size (or‘page size’) and end at addresses that areinteger multiples of [page size – 1]. If aPage Write command attempts to writeacross a physical page boundary, theresult is that the data wraps around to thebeginning of the current page (overwritingdata previously stored there), instead ofbeing written to the next page, as might beexpected. It is therefore necessary that theapplication software prevent page writeoperations that would attempt to cross apage boundary.

6.2Page Write

The write-control byte, word address and the first databyte are transmitted to the 24AA014H/24LC014H in thesame way as in a byte write. But instead of generatinga Stop condition, the master transmits up to 15additional data bytes to the 24AA014H/24LC014H thatare temporarily stored in the on-chip page buffer andwill be written into the memory once the master hastransmitted a Stop condition. Upon receipt of eachword, the four lower order Address Pointer bits areinternally incremented by one.

6.3Write Protection

The WP pin must be tied to VCC or VSS. If tied to VCC,half of the array will be write-protected (40h-7Fh). If theWP pin is tied to VSS, write operations to all addresslocations are allowed.

FIGURE 6-1:

Bus ActivityMasterSDA LineBus Activity

STARTS

BYTE WRITE

ControlByte

WordAddress

Data

STOPP

ACK

FIGURE 6-2:

Bus ActivityMasterSDA LineBus Activity

STARTS

PAGE WRITE

ControlByte

WordAddress (n)

STOPP

ACK

Data (n)Data (n +1)Data (n + 15)

Preliminary

DS22077B-page 9

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24AA014H/24LC014H

7.0

ACKNOWLEDGE POLLING

FIGURE 7-1:

Since the device will not acknowledge during a writecycle, this can be used to determine when the cycle iscomplete (this feature can be used to maximize busthroughput). Once the Stop condition for a writecommand has been issued from the master, the deviceinitiates the internally-timed write cycle and ACK pollingcan be initiated immediately. This involves the mastersending a Start condition followed by the control bytefor a Write command (R/W = 0). If the device is stillbusy with the write cycle, no ACK will be returned. If noACK is returned, the Start bit and control byte must bere-sent. If the cycle is complete, the device will returnthe ACK and the master can then proceed with the nextRead or Write command. See Figure7-1 for a flowdiagram of this operation.

ACKNOWLEDGE POLLING FLOW

Send

Write Command

Send StopCondition toInitiate Write Cycle

Send Start

Send Control Bytewith R/W = 0

Did DeviceAcknowledge(ACK = 0)?Yes

NextOperation

DS22077B-page 10

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分销商库存信息:

MICROCHIP24AA014H-I/SN24AA014HT-I/MNY24LC014HT-I/SN24AA014H-I/ST24LC014HT-I/MS24LC014HT-E/SN24LC014HT-E/ST24LC014H-E/P

24LC014H-I/MS24AA014H-I/P24AA014H-I/MS24AA014HT-I/MS24LC014HT-I/ST24LC014H-E/MS24LC014HT-E/MS24LC014H-I/SN

24LC014HT-I/MNY24AA014HT-I/SN24LC014H-I/ST24AA014HT-I/ST24LC014H-E/SN24LC014H-E/ST24LC014HT-E/MNY24LC014H-I/P

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24AA014H-ISN;24LC014H-IMS;24LC014HT-IMNY;24AA014HT-IMNY;24AA014H-IP;中文规格书,Datasheet资料