专利名称：System on a chip for packet processing发明人：Mark D. Hayter,Shailendra S. Desai,Daniel W.
Dobberpuhl,Kwong-Tak A. Chui
申请号：US09861188申请日：20010518公开号：US07287649B2公开日：20071030
专利附图：
摘要：A packet processing system may include a processor, a cache, a memorycontroller, and at least one packet interface circuit integrated into a single integratedcircuit. In one embodiment (which may be used in integrated or non-integrated systems),
the packet interface circuit is configured to cause allocation in the cache of a portion of areceived packet. In one embodiment (which may be used in integrated or non-integratedsystems), the memory controller may be configured to selectively block memorytransactions. Particularly, the memory controller may implement at least two blocksignals, one for the packet interface circuit and one for other devices. The block signalsmay be used to control the initiation of memory transactions when the memorycontroller's input queue is approaching fullness.
申请人：Mark D. Hayter,Shailendra S. Desai,Daniel W. Dobberpuhl,Kwong-Tak A. Chui
地址：Menlo Park CA US,San Jose CA US,Menlo Park CA US,Cupertino CA US
国籍：US,US,US,US
代理机构：Garlick Harrison & Markison
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