专利名称：INTEGRATED CIRCUIT ARRANGEMENT WITH
ESD-RESISTANT CAPACITOR ANDCORRESPONDING METHOD OFPRODUCTION
发明人：ESMARK, KAI,GOSSNER, HARALD,RUSS,
CHRISTIAN,SCHNEIDER, JENS
申请号：EP05701625.5申请日：20050131公开号：EP1714322A2公开日：20061025
摘要：The invention relates to a circuit arrangement (10) that comprises a capacitor(12) inside an n-trough (20). A specific polarization of the capacitor (12) makes sure that adepletion zone is formed in the trough (20) and the capacitor (12) has a high ESDresistance. An optionally present auxiliary doped layer (26) ensures a high areacapacitance of the capacitor despite high ESD resistance.
申请人：INFINEON TECHNOLOGIES AG
地址：St.-Martin-Strasse 53 81669 München DE
国籍：DE
代理机构：Kindermann, Peter
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