VOLTAGE-CONTROLLED OSCILLATOR, PHASE-LOCKED LOOP (

专利名称：VOLTAGE-CONTROLLED OSCILLATOR,

PHASE-LOCKED LOOP (PLL) CIRCUIT, ANDCLOCK GENERATOR

发明人：Jae-Hyun Park,Jong-Shin Shin申请号：US12479132申请日：20090605

公开号：US20100052746A1公开日：20100304

专利附图：

摘要：A voltage-controlled oscillator includes a voltage regulator, and a delay unit.The voltage regulator independently receives a first oscillation control signal and a

second oscillation control signal to provide a regulated voltage signal which is

represented by a regular ratio of combination of the first and second oscillation controlsignals, and the regulated voltage signal is feedback to the voltage regulator. The delayunit generates an output signal having a frequency varying in response to the regulatedvoltage signal.

申请人：Jae-Hyun Park,Jong-Shin Shin

地址：Seoul KR,Anyang-si KR

国籍：KR,KR

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