Preliminary W6662CF
SCANNER ANALOG FRONT END
1. GENERAL DESCRIPTION
The W6662 is a highly integrated CCD/CIS analog front end signal processor. It provides thecomponents required for all necessary front-end signal process of a CCD/CIS scanner, including a 3-channel input clamp circuit for correlated double sampling (short as CDS) mode, a multiplexer to mux3-channel inputs to a correlated double sampling (CDS) circuit, a programmable offset adjusted andgain controlled amplifier, a 12-bit analog-to-digital converter.
CDS or S&H (sample and hold) of operation modes can be chosen. The device configuration isprogrammed via 3-wire or 4-wired interface, operation modes, offset and gain value of each channelcan be programmed.
2. FEATURES
•12-bit A/D Converter•No Missing Code Guaranteed
•Three channels analog input with clamp circuit individually•Integrated Correlated Double Sampler (CDS)•Supports Contact Image Sensors (CIS)
•Accept CCD/CIS sensor with three channel or single channel analog out•External offset voltage input for CIS reference voltage
•Built-in bandgap reference circuit for CDS mode and A/D Converter
•Integrated 6-bit Programmable Gain Amplifier (PGA) with 3-channel register selected•Integrated 8-bit offset adjustment with 3-channel register selected•3 MHz sampling rate of offset/gain adjustment circuit•Three-wired or four-wired Serial Interface programmable•Registers readback capability•Low power CMOS device•Power down mode supported•3/5V digital I/O pin•Packageed in 48-pin QFP
Applications:
Flatbed ScannersSheetfeed ScannersFilm Scanners
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Publication Release Date: December 1998
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Preliminary W6662CF
3. PIN CONFIGURATION
DOUT11DOUT10DOUT938VRDBVRDTAVDDVRDBVRDTVRDCVREFVINRAVSSVINGAVSSVINBAVSSNCAVDDCISREFPAOUT123448474645444342414039AVDD3736353433AVSSOENNCNCAVSSDOUT8DOUT7DOUT6DOUT5DOUT4DOUT3DOUT2DOUT1DOUT0SENWinbond5678910111213323130292827262524W6662CF14151617181920212223Fig. 3-1 Pin Assignments.4. BLOCK DIAGRAMCISREFVREFVRDCVRDBVRDTBandgap Reference CircuitCDSSDI/SDIOADCCLKSDO/SMSCDSCK1DRVDDSEL0PAOUTNSEL1NCCDSCK2DRVSSSCLKOENGain/OffsetAdjust12-bitADCDOUT[11:0]VINRClampMUXCDSProcessVINGClampI/P MUXCtrlDACMUXMUXWeakDrivePAOUTPAOUTNSCLKVINBClampConfigurationRegisterRGBRGBSerialI/O portcontrolSENSDI/SDIOSDO/SMSGainOffset RegistersRegistersCDSCK1CDSCK2SEL0SEL1ADCCLKFig. 4 The Block Diagram of W6662 Device.- 2 -元器件交易网www.cecb2b.com
Preliminary W6662CF
5. PIN DESCRIPTIONS
PIN10, 37, 44 4, 6, 8, 35, 42
45, 4647, 4812357111213141516191720212223242526:3438:4041
NAMEAVDDAVSSVRDTVRDBVRDCVREFVINRVINGVINBCISREFPAOUTPAOUTNCDSCK1CDSCK2ADCCLKDRVDDDRVSSSEL0SEL1SCLKSDI/SDIOSDO/SMSSENDOUT[0:8]DOUT[9:11]
OEN
TYPEAPAPAOAOAOAOAIAIAIAIAOAODIDIDIDPDPDIDIDIDI/DO
Analog Power Supply.Analog Ground.
Voltage Reference Decoupling (Top).Voltage Reference Decoupling (Bottom).Voltage Reference Decoupling (Center).Internal Reference Output.Analog Input, Red Channel.Analog Input, Green Channel.Analog Input, Blue Channel.
Reference Voltage Input when CIS input.
PGA Output, low speed analog monitor output for test only.PGA Output (negative), low speed analog monitor output fortest only.
CDS Clock 1 (Schmitt Trigger Input), Reset Level SamplingClock.
CDS Clock 2 (Schmitt Trigger Input), Data Level SamplingClock.
A/D Converter Sampling Clock (Schmitt Trigger Input).Digital Driver Power Supply.Digital Driver Ground.Channel Select bit 0.Channel Select bit 1.
Clock Input of Serial Interface (Schmitt Trigger Input).Serial Interface of Data Input or Serial Interface of DataInput/Output.
DESCRIPTION
DI, DOSerial Interface of Data Output, Serial Interface Mode
Select.DIDODODI
Enable Signal of Serial Interface, Active Low.Data Output Bit, DOUT0 is LSB.Data Output Bit, DOUT11 is MSB.Output Enable, Active Low.
Type: AP is Analog Power, AI is Analog Input, AO is Analog Output, DP is Digital Power, DI is Digital Input, DO is Digital
Output.
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Preliminary W6662CF
6. FUNCTIONAL DESCRIPTIONS
Figure 4 is the block diagram of W6662, it consists of three channel clamp circuit for CDS mode, amultiplexer to mux 3-channel inputs and outputs to a correlated double sampling (CDS), aprogrammable gain control and offset adjustment amplifier, a 12-bit analog-to-digital converter.Bandgap reference circuit generate voltage reference signals for input signals clampping andcorrelated sampling use (in CDS mode), for offset D/A converter and output A/D converter use. Theselect signals SEL1 and SEL0 are used to select the offset registers and gain registers, the inputchannels may be selected simultaneously.
6.1 Clamp Circuit
The capacitor between the output of CCD/CIS device and W6662 is used to block the DC voltage(even as high voltage). The clamp circuit is used to remove unwanted common-mode voltage in theinput pixel data and to get a maximum input signal span when the input is driven by CCD device asshown in Figure 6-1. The input pins of W6662 are clampped to a internal offset voltage while validpixel signal is input. The clamp switches at three channels of figure 6-1 are turn on wheneverCDSCK1 goes high. Figure 6-2 shows the waveform between output of CCD device and input ofW6662, the voltage change on the capacitor will be clampped.The value of input capacitor is calculated as follows:
tCLP
CMAX =
(RON + RCCDS) × ln (VC/VCLPTolerance)
IBIAS × tC2I
CMIN =
dV
where
CMAX is the maximum capacitor value.CMIN is the minimum capacitor value.
tCLP is the high pulse width of the CDSCK1 clock input.
RON is switch resistance during clampping and is equivalent to 5K.RCCDS is the source resistance of CCD device.
VC is the voltage change on the input capacitor must be clampped.VCLPTolerance is the tolerance voltage error at the end of clampping.IBIAS is the input leakage current on the input of the W6662 device.dV is the maximum voltage drift on the input of the W6662 device.
tC2I is the time stamp from the end of clampping point to the acture input data sampling point, equalto tC2S + tSPD + tACD or may be approximated as conversion time tCVR.
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If input capacitor value is specified as CIN, the following is the equation to calculate how many linesare required before the capacitor settles to the desired accuracy after power is up:
(RON + RCCDS) × CINLN = ln (VOFS/VCLPTolerance )PIXN × tCLPwhereLN is line number.PIXN is the total pixel number in one line.CIN is the input capacitor value, 0.01 µF is suggestion value.VOFS is the internal offset voltage to be clampped on the input terminal of the input capacitor.CCD DeviceRCCDS(Pixel n)CINW6662IBIASInput to MUXVC(Pixel n+1)Outputsignalfrom CCDVDATAntCLPVDATAn+10.01uFRON = 5Kon whenCDSCK1= highVOFSInputsignal to W6662VOFSVDATAnVCVCLPToleranceVDATAn+1Fig. 6-1 Equivalent Circuit of Clampping.6.2 MUX and Channel SelectFig. 6-2 CCD Input Clamp Waveform.The analog input signal may be three channels or single channel and is specified in configurationregister. Three channel input or single channel input are described as follows:The three channel input is used for red, green and blue analog signal input, selected by SEL1 andSEL0 signals. The channel select signals SEL1 and SEL0 may be 01, 10, 11 and listed as follows:SEL1 = 0, SEL0 = 1 is red channel input selected, red channel of gain register and offset register alsoselected.
SEL1 = 1, SEL0 = 0 is green channel input selected, green channel of gain register and offset registeralso selected.
SEL1 = 1, SEL0 = 1 is blue channel input selected, blue channel of gain register and offset registeralso selected.
SEL1 = 0, SEL0 = 0 is reserved.
The one channel input is used for black and white CCD/CIS sensor or multiplexed color CCD/CISsensor output. Any channel input of red, green or blue can be used, other un-used analog input musttight to VSS in S & H mode. The channel select signals SEL1 and SEL0 is used to select offsetregister and gain register only and may be 01, 10, 11, described as follows:
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Preliminary W6662CF
SEL1 = 0, SEL0 = 1 is red channel of gain register and offset register selected.SEL1 = 1, SEL0 = 0 is green channel of gain register and offset register selected.SEL1 = 1, SEL0 = 1 is blue channel of gain register and offset register selected.SEL1 = 0, SEL0 = 0 is reserved.
6.3 CDS vs S&H Mode
\"CDS\" stands for \"correlated double sampling\". It is used to reduce noise generated in CCD sourceand to decrease the sampling error which induced from clampping voltage error. CDS takes two stepto sample a CCD's output pixel. In the first step, the reset level of CCD output is sampled and hold byS/H1 at the falling edge of CDSCK1 signal. In the second step, the data signal of CCD output issampled and hold by S/H2 at the falling edge of CDSCK2 signal. The CDS output voltage is obtainedfrom the voltage difference of the outputs of S/H1 and S/H2.
In S&H mode, the data signal of CIS output is sampled and hold by S/H1 at the falling edge ofCDSCK2 signal and the output voltage is obtained from the voltage difference of the outputs of S/H1and CISREF pin. Figure 6-3 shows the equivalent circuits of CDS and S&H mode processing.FromI/PMUXS/H1CDSCK1+To Gain/OffsetAdjustS/H2-(a) CDS Mode.CDSCK2FromI/PMUXFromCISREFpinS/H1CDSCK2+To Gain/OffsetAdjust-(b) S&H Mode.Fig. 6-3 The Equivalent Circuit of CDS and S&H Mode.6.4 Gain/Offset Adjustment
The analog input signal after CDS or S&H processed is amplified by PGA gain adjustment and thenshifted by offset value. The offset value will not affected by the PGA gain adjustment.
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Preliminary W6662CF
PGA Gain Adjustment
\"PGA\" stands for \"programmable gain amplifier\A/D converter\" input signals. The gain value is converted from PGA_code of gain register and isselected by channel select SEL1 and SEL0. The gain formula is:
PGA_code
analog gain = 1 +
12
PGA_code = 0−63 and the gain = 1−6.25.
Offset Adjustment
The analog signal level can be shifted by offset level and to get maximum linear region. The offsetlevel is converted from offset value by internal D/A converter and the offset value is selected bychannel select SEL1 and SEL0.
The mapping between offset register code and offset value is as follows:
OFFSET REGISTER1111 1111 (LSB)::
1000 00011000 00000000 00000000 0001::
0111 1111
OFFSET VALUE+200 mV::
+1.6 mV0.0 mV0.0 mV-1.6 mV::
-200 mV
6.5 Analog Monitor
The analog differential signal of PAOUT and PAOUTN is used to monitor the output waveform aftergain and offset adjustment process. The CCD or CIS pixel rate must operate below or equal 1MHzand at most one probe loading on the PAOUT and PAOUTN to get a correct voltage output. In normaloperation, the PAOUT and PAOUTN must be turned off by writting a specified bit on the configurationregister to avoid the interference of noise and extra capacitance loading.
6.6 Internal Registers
The registers in the W6662 is configuration register, three channel offset registers and three channelgain registers, these registers are addressed by A2, A1 and A0. The registers can be read or modifiedthrough 3-wired or four-wired serial interface. During address phase, if SDO/SMS pin is low, three-wired is selected, the three-wired interface are SEN, SCLK and SDIO signals, if SDO/SMS pin ishigh, four-wired interface is selected, the four-wired interface are SEN, SCLK SDI and SDO signals.Figure 6-4 shows the setting of the serial interface. For three-wired interface setting, the SDO/SMSpin must connected to VSS. For four-wired interface, it only need to connect a pull high resistor on theSDO/SMS pin. The signal format on the serial interface is listed as follows:
Publication Release Date: December 1998
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Preliminary W6662CF
R/W A0 A1 A2 -- -- -- -- D0 D1 D2 D3 D4 D5 D6 D7 Address phaseData phaseR/W is read (high) or write (low) command to access the register.A0, A1 and A2 is the address select bits of the register.
D0 throuth D7 is the data bit of the register, D7 is MSB and D0 is LSB.The address of the registers is:
A200001111
A100110011
A001010101
REGISTER
Configuration RegisterRed PGA RegisterGreen PGA RegisterBlue PGA RegisterRed Offset RegisterGreen Offset RegisterBlue Offset RegisterReserved
Configuration Register
The bit definition of configuration register is:
A. Configuration mode (wake up and configuration)bit 0 =0: 1.5V input span.
1: 3.0V input span.
bit 1 =0: S&H mode.
1: CDS mode.
bit [3:2] = 0 0: Red channel input only.
0 1: Green channel input only. 1 0: Blue channel input only.
1 1: Three channels input and selected by SEL1 and SEL0 signals.
bit 4 =Reserved (must set to 0).bit 5 =0: PAOUT and PAOUTN enable.
1: PAOUT and PAOUTN disable.
bit 6 =Reserved (must set to 0).bit 7 =0.
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Preliminary W6662CF
B. Power down modebit [6:0] = don't care.bit 7 = 1.
The CDSCK1, CDSCK2, ADCCLK and SCLK must hold at stable state after power down mode hasbeen configured to ensure the W6662 is in low power state. The system must wait at least 10 mS toensure that the device is power up completedly if the configuration register is programmed with bit 7= 0.
PGA Registers
The mapping of PGA registers and PGA_code is:bit [5:0]PGA_code, bit 5 is MSB, bit 0 is LSB.bit [7:6]reserved (must set to 0).The offset registers are described in PGA gain/offset adjustment section.W6662SCLKSENSDIOSMSchip selectMicro-controllerorSystem ControllerorCore ChipMay drive another peripherals(a). Three-wired Interface Mode Selected.W6662Micro-controllerorSystem ControllerorCore ChipSCLKSENSDISDODRVDDchip select(b). Four-wired Interface Mode Selected.May drive another peripheralsFig. 6-4 Configuration Serial Interface Modes.- 9 -
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Preliminary W6662CF
7. ELECTRICAL CHARACTERISTICS
7.1 Maximum Ratings*
PARAMETER
Supply Voltage with respect to AVSS (at AVDD pin)Supply Voltage with respect to DRVSS (at DRVDDpin)
Voltage on any pin other than VAVDD suppliesVoltage on any pin other than VDRVDD suppliesCurrent at any pin other than suppliesStorage Temperature
* Exceeding these values may cause permanent damage.
SYMBOLVAVDDVDRVDD
RATING-0.3 to 6-0.3 to 6-0.3 to VAVDD + 0.3-0.3 to VDRVDD + 0.3
0 to 10
UNITSVVVVmA°C
TST-65 to 150
7.2 Recommended Operating Conditions
PARAMETER
Operation Voltage (referenced to AVSS pin)Operation Voltage (referenced to DRVSS pin)Operation Temperature
SYMBOLVAVDDVDRVDDTOP
RATING4.75 to 5.253.0 to 5.250 to 70
UNITVV°C
7.3 Power Supply Characteristics
PARAMETERStandby Supply CurrentOperating Supply Current
production testing.
Test 1: All input pins are VDD or VSS, include CDSCK1, CDSCK2, ADCCLK and SCLK, OEN and SEN are VDD, configure as
power down mode, output without loading.Test 2: No analog input, CDS mode configured, 2 MHz pixel rate, PAOUT and PAOUTN disabled and output without loading.
CONDITIONPower Supply(VDD = 5.0V)
SYMBOLIDDQIDD
MIN.
TYP‡30
MAX.0.140
UNITSmAmA
TESTTest 1Test 2
‡: Typical figure are at VDD = 5V and temperature = 25° C and are for design aid only, not guaranteed and not subject to
7.4 Digital Characteristics
PARAMETER
Output High Sourcing CurrentOutput Low Sinking CurrentHigh Level Input VoltageLow Level Input VoltageSchmitt Input High ThresholdVoltage
CONDITION(VDRVDD = 5V)(VDRVDD = 5V)(VDRVDD = 5V)(VDRVDD = 5V)(VDRVDD = 5V)
SYM.IOHIOLVIHVILVT+
MIN.0.50.52.0
0.82.2
TYP‡MAX.
UNITSNOTESmAmAVVV
12334
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Preliminary W6662CF
7.4 Digital Characteristics, continued
PARAMETER
Schmitt Input Low ThresholdVoltageInput CurrentInput Capacitance
production testing.
CONDITION(VDRVDD = 5V)
SYM.VT-IinCin
MIN.0.8
TYP‡MAX.UNITSNOTESV
4
1
10
µApF
‡: Typical figure are at VDD = 5V and temperature = 25° C and are for design aid only, not guaranteed and not subject to
Notes:
1: VOH = 0.9 VDRVDD.2: VOL = 0.1 VDRVDD.
3. All digital input pin, CDSCK1, CDSCK2, ADCCLK and SCLK are exclusive.4. CDSCK1, CDSCK2, ADCCLK and SCLK schmitt trigger input pins.
7.5 Analog Characteristics (measures from analog input to ADC output)
PARAMETER
Analog to Digital ConverterMaximum Conversion RateResolution
Integral NonlinearityDifferential NonlinearityGain ErrorOffset ErrorPGA & Offset DACPGA Gain RangePGA Gain ResolutionOffset RangeOffset ResolutionBandgap ReferenceVoltage Reference Tolerance(VREF = 1.5V or 0.75V)Analog Input and OutputLinear Region of Analog InputInput CapacitanceInput Leakage CurrentTotal Output Noise at PGA
VinCinIBIAS
4
0
10
0.013
VpFµALSB
VREF
+/-1.5%
+/-2.0%
VAVDD = 5.0V
GGRESOFSOFSRES
-200
256
1
64
2006.25
V/VstepsmVsteps
Note 2VAVDD = 5.0V
Note 2
INLDNLADGERRADOFERR
SPS
3
12+/- 4+/- 12.7%2.7%
MHzBitsLSBLSBFSRFSR
Note 1Note 1
SYM.
MIN.
TYP‡MAX.
UNITS
TEST CONDITIONS
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7.5 Analog Characteristics (measures from analog input to ADC output), continued
PARAMETER
Signal to Noise Ratiofrom analog I/P to ADC O/P
SYM.SNR
MIN.
TYP‡57
MAX.UNITSdB
TEST CONDITIONS
Note 3
‡: Typical figure are at VDD = 5V and temperature = 25° C and are for design aid only, not guaranteed and not subject to
production testing.
Notes:
1: 3V input span configured, PGA gain = 1, offset = 0 and measures from analog input to ADC output.2: All steps of PGA gain and offset are monotonic.
3. 3V input span configured and analog 3V signal range.
7.5.1 Analog Characteristics (measures from ADC input to ADC output)
PARAMETER
Analog to Digital ConverterMaximum Conversion RateResolution
Integral NonlinearityDifferential Nonlinearity
INLDNL
+/- 1.5+/- 1
SPS
3
12
MHzBitsLSBLSB
NoteNote
SYM.
MIN.
TYP.
MAX.
UNITS
TEST CONDITIONS
Note: This is measured on the engineer sample and do not subject to production testing.
7.6 Timing Characteristics
PARAMETER
Clock Input RequirementConversion Rate
ADCCLK High pulse widthADCCLK Low pulse widthClamp pulse widthSample data pulse widthClamp to Sample
Sample data to ADC ConvertADC Convert to ClampAnalog signal Capture Delay ofCDS clocks
tCVRtADCHtADCLtCLPtSPDtC2StS2ADtS2CtACD
33216616640402080tS2AD+2010
nSnSnSnSnSnSnSnSnS
SYM.
MIN.
TYP.
MAX.
UNITS
NOTES
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Preliminary W6662CF
7.6 Timing Characteristics, continued
PARAMETER
Data OutputDigital Output DelayOutput Enable to Data DelayOutput Disable to Data tri-stateDigital Output LatencySerial Interface
Maximum SCLK FrequencySEN to SCLK set-up timeSCLK to SEN hold timeSDI input to SCLK set-up timeSCLK to SDI input hold timeSCLK falling to SDO outputenable time
SDO output delay timeSEN to SDO output tri-statedelay time
SYM.tDODtOEDtODZ
MIN.TYP.MAX.4020203
UNITSnSnSnSADCCLKcycles
MHznSnSnSnS
NOTES
fSCLKtSEStSEHtSIStSIHtSOEtSODtSOZ
10101510
24
101510
nSnSnS
Analoginput(PIXn)tACDtCLPtACD(PIXn+1)(PIXn+2)(PIXn+3)(PIXn+4)tCVRCDSCK1tC2StS2CtSPDCDSCK2tADCLtS2ADADCCLKtADCHtDOD(PIXn-4)Latency0(PIXn-3)1(PIXn-2)2(PIXn-1)(PIXn)3DOUT(PIXn-5)Fig. 7-1 Timing of CDS Mode.- 13 -
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(PIXn)(PIXn+1)(PIXn+2)(PIXn+3)(PIXn+4)AnaloginputtACDCDSCK1tSPDtCVRCDSCK2tADCLtS2ADADCCLKtADCHtDOD(PIXn-4)Latency0(PIXn-3)1(PIXn-2)2(PIXn-1)(PIXn)3DOUT(PIXn-5)Fig. 7-2 Timing of S&H Mode.ADCCLKtDODhigh-ZtOEDtODZDOUTOENFig. 7-3 Output Enable Timing.SCLKtSIStSIH1/fSCLKtSISA2D0D1D2D3D4D5D6tSIHD7SDI/SDIOA0A1SENtSEStSEHFig. 7-4 Serial Interface Write Timing (3-wired or 4-wired Interface).- 14 -
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Preliminary W6662CF
SCLKtSIStSIH1/fSCLKA0A1A2tSOEtSIShigh-ZD0D1D2D3D4D5D6D7tSOZtSODSDIO(input)SDIO(output)high-ZSENtSEStSEHFig. 7-5 Serial Interface Read Timing in 3-Wired Interface (SMS = low).SCLKtSIStSIH1/fSCLKA0A1A2tSOEtSIStSODD1D2D3D4D5D6D7tSOZD0D1D2D3D4D5D6D7SDISDO(output)SMS(input)SENtSEShigh-ZD0(Note: SDO and SMS at the same pin)pull-highdriven by SDOtSEHFig. 7-6 Serial Interface Read Timing in 4-Wired Interface Mode.- 15 -
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8. APPLICATION CIRCUITS
8.1 System Application
Figure 8-1 is the application block diagram of scanner, the photo sensor may be CCD device or CISdevice with single channel or three-channel analog output. The ASIC is used to generate the requestsignal of photo sensor, W6662, motor control and other mechanical/electric interface. The memorybuffer is used to temporary store the image data and the data will be transfered to the host throughEPP port or other interface as SCSI. If micro controller is included, some control sequence, photosensor calibration or image data procession can be completed without the aid of the host.
MemoryBufferto/fromother mechanicalcontrol and senorPhotoSensorW6662ScannerASICHostInterfaceMicroController(optional)Fig. 8-1 System Application.- 16 -
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8.2. Decoupling Circuit
Figure 8-2 shows the decoupling capacitor request on the W6662 system board to reduce noise anddistortion, 0.1 µF capacitor must as near to the pin as possible. The analog power source and digitalpower source (DRVDD) had better regulated by different regulator, the analog ground and digitalground (DRVSS) must separated and must connected only at one point near the power supplier. Allthe analog power pins must connected as short as possible and all the analog ground pins mustconnected as short as possible on the PC board. Termination resistor must added near the W6662chip on the CDSCK1, CDSCK2 and ADCCLK input pin.
(Analog Part)VRDT10uF0.1uF+(Digital Part)VRDTVDRBVRDBW6662(other pins are not shown)CDSCK1RtermCDSCK20.1uF0.1uF0.1uFVRDCRterm1uFVREF+ADCCLKRterm0.1uF0.1uFCISREFDRVDDDRVDDDRVSS(near power source)AVDD10uF+AVDD0.1uF0.1uF+10uFAVSSFig. 8-2 Decoupling Capacitor Circuit of W6662 Device.- 17 -
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9. PACKAGE DIMENSIONS
48L QFP (10 x 10 x 2.0 mm footprint 5.0 mm)
HDD4837136EHE122513eb24c2ALL1θDetail FSeating PlaneSee Detail FyA1SymbolDimension in inchMin.Nom.Max.Dimension in mmMin.Nom.Max.AA1A2bcDEeHDHELL1yθ0.900.0040.0080.0780.0100.0040.3900.3900.0130.0060.3940.394.0290.5820.5820.5900.5900.0660.0980.00401000.5980.59814.8014.800.0180.0080.3980.3980.250.109.99.90.0120.100.202.000.330.1510.0010.000.7515.015.01.702.502.300.300.450.2010.110.115.2015.200.1010- 18 -
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Preliminary W6662CF
HeadquartersWinbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II,No. 4, Creation Rd. III,
123 Hoi Bun Rd., Kwun Tong,Science-Based Industrial Park,
Kowloon, Hong KongHsinchu, Taiwan
TEL: 852-27513100TEL: 886-3-5770066
FAX: 852-27552064FAX: 886-3-5792646
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-27197006
Winbond Electronics North America Corp.Winbond Memory Lab.
Winbond Microelectronics Corp.Winbond Systems Lab.
2727 N. First Street, San Jose,CA 95134, U.S.A.TEL: 408-9436666FAX: 408-5441798
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,Taipei, Taiwan
TEL: 886-2-27190505FAX: 886-2-27197502
Note: All data and specifications are subject to change without notice.
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